ARM ARM1176JZF-S Technical Reference Manual page 608

ARM DDI 0301H
ID012310
Name
ARREADYRW
BRESPD[1:0]
BRESPP[1:0]
BRESPRW[1:0]
BVALIDD
BVALIDP
BVALIDRW
RDATAD[63:0]
RDATAI[63:0]
RDATAP[31:0]
RDATARW[63:0
]
RLASTD
RLASTI
RLASTP
RLASTRW
RRESPD[1:0]
RRESPI[1:0]
RRESPP[1:0]
RRESPRW[1:0]
RVALIDD
RVALIDI
RVALIDP
RVALIDRW
WREADYD
WREADYP
WREADYRW
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Table 17-2 AXI signals (continued)
Minimum input delay Maximum input delay%
Clock uncertainty 50
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 50
Clock uncertainty 50
Clock uncertainty 50
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 70
Clock uncertainty 50
Clock uncertainty 50
Clock uncertainty 50
Clock uncertainty 50
Clock uncertainty 50
Clock uncertainty 50
Clock uncertainty 50
AC Characteristics
17-4