Figure 4-13 Store Word, Big-Endian - ARM ARM1176JZF-S Technical Reference Manual

4.3.14 Load double, load multiple, load coprocessor (little-endian, E = 0)
4.3.15 Load double, load multiple, load coprocessor (big-endian, E=1)
4.3.16 Store double, store multiple, store coprocessor (little-endian, E=0)
4.3.17 Store double, store multiple, store coprocessor (big-endian, E=1)
ARM DDI 0301H
ID012310
If strict alignment fault checking is enabled and Address bits [1:0] are not zero, then a Data
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register.
The access is treated as a series of incrementing aligned word loads from memory. The data is
treated as load word data, see Load word, little-endian on page 4-10, where the lowest two
address bits are zeroed. If strict alignment fault checking is enabled and effective Address
bits[1:0] are not zero, then a Data Abort is generated and the MMU returns an Alignment fault
in the Fault Status Register.
The access is treated as a series of incrementing aligned word loads from memory. The data is
treated as load word data, see Load word, big-endian on page 4-11, where the lowest two
address bits are zeroed. If strict alignment fault checking is enabled and effective Address
bits[1:0] are not zero, then a Data Abort is generated and the MMU returns an Alignment fault
in the Fault Status Register.
The access is treated as a series of incrementing aligned word stores to memory. The data is
treated as store word data, see Store word, little-endian on page 4-11, where the lowest two
address bits are zeroed. If strict alignment fault checking is enabled and effective Address
bits[1:0] are not zero, then a Data Abort is generated and the MMU returns an Alignment fault
in the Fault Status Register.
The access is treated as a series of incrementing aligned word stores to memory. The data is
treated as store word data, see Store word, big-endian, where the lowest two address bits are
zeroed. If strict alignment fault checking is enabled and effective Address bits[1:0] are not zero,
then a Data Abort is generated and the MMU returns an Alignment fault in the Fault Status
Register.
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Unaligned and Mixed-endian Data Access Support
Register
31 23 15 7
B0 B1 B2 B3
Memory
7
Address
A[31:0]
0
+1
+2
+3

Figure 4-13 Store word, big-endian

0
B0 msbyte
B1
B2
B3 lsbyte
4-12