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Reserved for Interrupt6
Reserved for Interrupt5
Reserved for Interrupt4
Reserved for Interrupt3
Reserved for Interrupt2
Reserved for Interrupt1
Interrupt0
Reserved for Mailbox31
Reserved for Mailbox30
Reserved for Mailbox29
Reserved for Mailbox28
Reserved for Mailbox27
Reserved for Mailbox26
Reserved for Mailbox25
Reserved for Mailbox24
Reserved for Mailbox23
Reserved for Mailbox22
Reserved for Mailbox21
Reserved for Mailbox20
Reserved for Mailbox19
Reserved for Mailbox18
Reserved for Mailbox17
Reserved for Mailbox16
Reserved for Mailbox15
Reserved for Mailbox14
Reserved for Mailbox13
Reserved for Mailbox12
Reserved for Mailbox11
Reserved for Mailbox10
Reserved for Mailbox9
Reserved for Mailbox8
Reserved for Mailbox7
Reserved for Mailbox6
Reserved for Mailbox5
Reserved for Mailbox4
Reserved for Mailbox3
Reserved for Mailbox2
Reserved for Mailbox1
Mailbox0
3-4
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0x830
0x828
0x820
0x818
0x810
0x808
0x800
0x7C0
0x780
0x740
0x700
0x6C0
0x680
0x640
0x600
0x5C0
0x580
0x540
0x500
0x4C0
0x480
0x440
0x400
0x3C0
0x380
0x340
0x300
0x2C0
0x280
0x240
0x200
0x1C0
0x180
0x140
0x100
0x0C0
0x080
0x040
0x000
Figure 3-2 on page 3-5 shows the register map for Mailbox0.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
PrimeCell Identification Register 3
PrimeCell Identification Register 2
PrimeCell Identification Register 1
PrimeCell Identification Register 0
Peripheral Identification Register 3
Peripheral Identification Register 2
Peripheral Identification Register 1
Peripheral Identification Register 0
Reserved
Integration Test Output Register
Integration Test Control Register
Reserved
Configuration Status Register
Reserved for Interrupt31
Reserved for Interrupt30
Reserved for Interrupt29
Reserved for Interrupt28
Reserved for Interrupt27
Reserved for Interrupt26
Reserved for Interrupt25
Reserved for Interrupt24
Reserved for Interrupt23
Reserved for Interrupt22
Reserved for Interrupt21
Reserved for Interrupt20
Reserved for Interrupt19
Reserved for Interrupt18
Reserved for Interrupt17
Reserved for Interrupt16
Reserved for Interrupt15
Reserved for Interrupt14
Reserved for Interrupt13
Reserved for Interrupt12
Reserved for Interrupt11
Reserved for Interrupt10
Reserved for Interrupt9
Reserved for Interrupt8
Reserved for Interrupt7
Figure 3-1 IPCM register map
0xFFC
0xFF8
0xFF4
0xFF0
0xFEC
0xFE8
0xFE4
0xFE0
0xF08
0xF04
0xF00
0x904
0x900
0x8F8
0x8F0
0x8E8
0x8E0
0x8D8
0x8D0
0x8C8
0x8C0
0x8B8
0x8B0
0x8A8
0x8A0
0x898
0x890
0x888
0x880
0x878
0x870
0x868
0x860
0x858
0x850
0x848
0x840
0x838
ARM DDI 0306B
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