Table 3-14 Processor Feature Register 1 Bit Functions; Figure 3-15 Processor Feature Register 1 Format; Table 3-15 Results Of Access To The Processor Feature Register 1 - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[31:28] -
[27:24] -
[23:20] -
[19:16] -
[15:12] -
[11:8] Microcontroller programmer's model
[7:4] Security extension
[3:0] Programmer's model
ARM DDI 0301H
ID012310
31 28 27 24 23
Reserved Reserved
Table 3-14 lists how the bit values correspond with the Processor Feature Register 1 functions.
Table 3-15 lists the results of attempted access for each mode.

Table 3-15 Results of access to the Processor Feature Register 1

Secure Privileged
Read Write
Data Undefined exception
To use the Processor Feature Register 1 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c0, c1, 1 ;Read Processor Feature Register 1
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
20 19 16 15
Reserved Reserved Reserved
Microcontroller programmer's model
Security extension
Programmer's model

Figure 3-15 Processor Feature Register 1 format

Table 3-14 Processor Feature Register 1 bit functions

Function
Reserved. RAZ
Reserved. RAZ.
Reserved. RAZ.
Reserved. RAZ.
Reserved. RAZ.
Indicates support for the ARM microcontroller programmer's model.
0x0 , Not supported by ARM1176JZF-S processors.
Indicates support for Security Extensions Architecture v1.
, ARM1176JZF-S processors support Security Extensions
0x1
Architecture v1, TrustZone.
Indicates support for standard ARMv4 programmer's model.
0x1 , ARM1176JZF-S processors support the ARMv4 model.
Non-secure Privileged
Read
Data
System Control Coprocessor
12 11 8 7
User
Write
Undefined exception Undefined exception
4 3 0
3-28