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ARM DDI 0301H
ID012310
It is important to distinguish between the InstCompl flag and the Ready flag:
•
The InstCompl flag signals the completion of an instruction.
•
The Ready flag is the captured version of the InstCompl flag, captured at the Capture-DR
state. The Ready flag conditions the execution of instructions and the update of the ITR.
The following points apply to the use of scan chain 4:
•
When an instruction is issued to the core in Debug state, the PC is not incremented. It is
only changed if the instruction being executed explicitly writes to the PC. For example,
branch instructions and move to PC instructions.
•
If CP14 debug register c5 is a source register for the instruction to be executed, the
DBGTAP debugger must set up the data in the rDTR before issuing the coprocessor
instruction to the core. See Scan chain 5 on page 14-15.
•
Setting DSCR[13] the execute ARM instruction enable bit when the core is not in Debug
state leads to Unpredictable behavior.
•
The ITR is write-only. When going through the Capture-DR state, an Unpredictable value
is loaded into the shift register.
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Debug Test Access Port
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