Table 3-112 Dma Control Register Bit Functions; Figure 3-62 Dma Control Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.37 c11, DMA Control Register
Bits Field name
[31] TR
[30] DT
[29] IC
[28] IE
[27] FT
ARM DDI 0301H
ID012310
The purpose of the DMA Control Register for each channel is to control the operations of that
DMA channel. Table 3-112 lists the purposes of the individual bits in the DMA Control
Register.
The DMA Control Register is:
• in CP15 c11
• one 32-bit read/write register for each DMA channel common to Secure and Non-secure
worlds
• accessible in user and privileged modes.
Figure 3-62 shows the bit arrangement for the DMA Control Register.
31 30 29 28 27 26 25
T D I I F U
UNP/SBZ
R T C E T M
Table 3-112 lists how the bit values correspond with the DMA Control Register.
Function
Indicates target TCM:
0 = Data TCM, reset value
1 = Instruction TCM.
Indicates direction of transfer:
0 = Transfer from level two memory to the TCM, reset value
1 = Transfer from the TCM to the level two memory.
Indicates whether the DMA channel must assert an interrupt on completion of the DMA
transfer, or if the DMA is stopped by a Stop command, see c11, DMA enable registers on
page 3-110.
The interrupt is deasserted, from this source, if the processor performs a Clear operation on the
channel that caused the interrupt. For more details see c11, DMA enable registers on
page 3-110.
a
The U bit has no effect on whether an interrupt is generated on completion:
0 = No Interrupt on Completion, reset value
1 = Interrupt on Completion.
Indicates that the DMA channel must assert an interrupt on an error.
The interrupt is deasserted, from this source, when the channel is set to Idle with a Clear
operation, see c11, DMA enable registers on page 3-110:
0 = No Interrupt on Error, if the U bit is 0, reset value
1 = Interrupt on Error, regardless of the U bit
U bit set to 1 Interrupt on Error regardless of the value written to this bit.
Read As One, Write ignored
In the ARM1176JZF-S this bit has no effect.
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20 19
ST

Figure 3-62 DMA Control Register format

Table 3-112 DMA Control Register bit functions

a
. All DMA transactions on channels that have the
System Control Coprocessor
8 7 2 1 0
UNP/SBZ TS
3-112