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18.4
VFP11 coprocessor pipelines
18.4.1
FMAC pipeline
ARM DDI 0301H
ID012310
The VFP11 coprocessor has three separate instruction pipelines:
•
the Multiply and Accumulate (FMAC) pipeline
•
the Divide and Square root (DS) pipeline
•
the Load/Store (LS) pipeline.
Each pipeline can operate independently of the other pipelines and in parallel with them. Each
of the three pipelines shares the first two pipeline stages, Decode and Issue. These two stages
and the first cycle of the Execute stage of each pipeline remain in lockstep with the ARM11
pipeline stage but effectively one cycle behind the ARM11 pipeline. When the ARM11
processor is in the Issue stage for a particular VFP instruction, the VFP11 coprocessor is in the
Decode stage for the same instruction. This lockstep mechanism maintains in-order issue of
instructions between the ARM11 processor and the VFP11 coprocessor.
The three pipelines can operate in parallel, enabling more than one instruction to be completed
per cycle. Instructions issued to the FMAC pipeline can complete out of order with respect to
operations in the LS and DS pipelines. This out-of-order completion might be visible to you
when a short vector FMAC or DS operation generates an exception, and an LS operation begins
before the exception is detected. The destination registers or memory of the LS operation reflect
the completion of a transfer. The destination registers of the exceptional FMAC or DS operation
retain the values they had before the operation started. Parallel execution on page 21-20
describes it in more detail.
Except for divide and square root operations, the pipelines support single-cycle throughput for
all single-precision operations and most double-precision operations. Double-precision
multiply and multiply and accumulate operations have a two-cycle throughput. The LS pipeline
is capable of supplying two single-precision operands or one double-precision operand per
cycle, balancing the data transfer capability with the operand requirements.
Figure 18-1 on page 18-6 shows the structure of the FMAC pipeline.
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Introduction to the VFP coprocessor
18-5
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