Table 3-136 Performance Monitor Control Register Bit Functions - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[31:28] -
[27:20] EvtCount0
[19:12] EvtCount1
[11] X
[10] CCR
[9] CR1
[8] CR0
[7] -
[6] ECC
[5] EC1
[4] EC0
[3] D
ARM DDI 0301H
ID012310
Table 3-136 lists how the bit values correspond with the Performance Monitor Control Register.
Function
UNP/SBZ.
Identifies the source of events for Count Register 0.
Table 3-137 on page 3-135 lists the values, functions and EVNTBUS bit position for Count
Register 0. The reset value is 0.
Identifies the source of events for Count Register 1.
Table 3-137 on page 3-135 lists the values and the bit functions for Count Register 1. The reset
value is 0.
Enable Export of the events to the event bus to an external monitoring block, such as the ETM
to trace events:
0 = Export disabled, EVNTBUS held at
1 = Export enabled, EVNTBUS driven by the events.
Cycle Counter Register overflow flag:
0 = For reads No overflow, reset value.
For writes No effect.
1 = For reads, overflow occurred.
For writes Clear this bit.
Count Register 1 overflow flag:
0 = For reads No overflow, reset value.
For writes No effect.
1 = For reads, overflow occurred.
For writes Clear this bit.
Count Register 0 overflow flag:
0 = For reads No overflow, reset value.
For writes No effect.
1 = For reads overflow occurred.
For writes Clear this bit.
UNP/SBZ.
Used to enable and disable Cycle Counter interrupt reporting:
0 = Disable interrupt, reset value
1 = Enable interrupt.
Used to enable and disable Count Register 1 interrupt reporting:
0 = Disable interrupt, reset value
1 = Enable interrupt.
Used to enable and disable Count Register 0 interrupt reporting:
0 = Disable interrupt, reset value
1 = Enable interrupt.
Cycle count divider:
0 = Counts every processor clock cycle, reset value
1 = Counts every 64th processor clock cycle.
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Table 3-136 Performance Monitor Control Register bit functions

, reset value
0x0
System Control Coprocessor
3-134