Figure 3-71 Peripheral Port Memory Remap Register Format - ARM ARM1176JZF-S Technical Reference Manual

MRC p15, 0, <Rd>, c13, c0, 2
MCR p15, 0, <Rd>, c13, c0, 2
MRC p15, 0, <Rd>, c13, c0, 3
MCR p15, 0, <Rd>, c13, c0, 3
MRC p15, 0, <Rd>, c13, c0, 4
MCR p15, 0, <Rd>, c13, c0, 4
3.2.49 c15, Peripheral Port Memory Remap Register
ARM DDI 0301H
ID012310
• Opcode_2 set to:
— 2, User Read/Write Thread and Process ID Register
— 3, User Read Only Thread and Process ID Register
— 4, Privileged Only Thread and Process ID Register.
For example:
Reading or writing the thread and process ID registers has no effect on processor state or
operation. These registers provide OS support and must be managed by the OS.
You must clear the contents of all thread and process ID registers on process switches to prevent
data leaking from one process to another. This is important to ensure the security of secure data.
The reset value of these registers is 0.
The purpose of the Peripheral Port Memory Remap Register is to remap the memory attributes
to Non-Shared Device. This forces access to the peripheral port and overrides what is
programmed in the page tables. The remapping happens both with the MMU enabled and with
the MMU disabled, therefore you can remap the peripheral port even when you do not use the
MMU. The Peripheral Port Memory Remap Register has the highest priority, higher than that
of the Primary and Normal memory remap registers.
Table 3-132 on page 3-131 lists the purposes of the individual bits in the Peripheral Port
Memory Remap Register.
The Peripheral Port Memory Remap Register is:
• in CP15 c15
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-71 shows the arrangement of the bits in the register.
31
Base address
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;Read User Read/Write Thread and Proc. ID Register
;Write User Read/Write Thread and Proc. ID Register
;Read User Read Only Thread and Proc. ID Register
;Write User Read Only Thread and Proc. ID Register
;Read Privileged Only Thread and Proc. ID Register
;Write Privileged Only Thread and Proc. ID Register

Figure 3-71 Peripheral Port Memory Remap Register format

System Control Coprocessor
12 11 5
UNP/SBZ
4 0
Size
3-130