Table 8-63 Cacheable Write-Through Or Noncacheable Stm10; Table 8-64 Cacheable Write-Through Or Noncacheable Stm11 - ARM ARM1176JZF-S Technical Reference Manual

8.5.33 Cacheable Write-Through or Noncacheable STM10
8.5.34 Cacheable Write-Through or Noncacheable STM11
ARM DDI 0301H
ID012310
Table 8-62 Cacheable Write-Through or Noncacheable STM9 (continued)
An STM10 over the Data Read/Write Interface is split into two or three operations as shown in
Table 8-63.
An STM11 over the Data Read/Write Interface is split into two or three operations as shown in
Table 8-64.
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Address[4:0]
, word 3
0x0C
, word 4
0x10
, word 5
0x14
, word 6
0x18
, word 7
0x1C

Table 8-63 Cacheable Write-Through or Noncacheable STM10

Address[4:0] Operations
, word 0 STM8 to
0x00
, word 1 STM7 to
0x04
, word 2 STM6 to
0x08
, word 3 STM5 to
0x0C
, word 4 STM4 to
0x10
, word 5 STM3 to
0x14
, word 6 STM2 to
0x18
, word 7 STR to
0x1C

Table 8-64 Cacheable Write-Through or Noncacheable STM11

Address[4:0] Operations
, word 0 STM8 to
0x00
, word 1 STM7 to
0x04
, word 2 STM6 to
0x08
, word 3 STM5 to
0x0C
, word 4 STM4 to
0x10
, word 5 STM3 to
0x14
, word 6 STM2 to
0x18
, word 7 STR to
0x1C
Level Two Interface
Operations
STM5 to + STM4 to
0x0C
STM4 to + STM5 to
0x10
STM3 to + STM6 to
0x14
STM2 to + STM7 to
0x18
STR to + STM8 to
0x1C
+ STM2 to
0x00 0x00
+ STM3 to
0x04 0x00
+ STM4 to
0x08 0x00
+ STM5 to
0x0C 0x00
+ STM6 to
0x10 0x00
+ STM7 to
0x14 0x00
+ STM8 to
0x18 0x00
+ STM8 to + STR to
0x1C 0x00
+ STM3 to
0x00 0x00
+ STM4 to
0x04 0x00
+ STM5 to
0x08 0x00
+ STM6 to
0x0C 0x00
+ STM7 to
0x10 0x00
+ STM8 to
0x14 0x00
+ STM8 to + STR to
0x18 0x00
0x1C + STM8 to 0x00 + STM2 to
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
8-33