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Chapter 8
Level Two Interface
The processor is designed to be used within larger chip designs using the Advanced Microcontroller
Bus Architecture (AMBA) AXI protocol. The processor uses the level two interface as its interface
to memory and peripherals. This chapter describes the features of the level two interface not
covered in the AMBA AXI Protocol Specification
The chapter contains the following sections:
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ARM DDI 0301H
ID012310
About the level two interface on page 8-2
Synchronization primitives on page 8-6
AXI control signals in the processor on page 8-8
Instruction Fetch Interface transfers on page 8-14
Data Read/Write Interface transfers on page 8-15
Peripheral Interface transfers on page 8-37
Endianness on page 8-38
Peripheral Interface transfers on page 8-37.
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