System Control Processor Registers - ARM ARM1176JZF-S Technical Reference Manual

3.2

System control processor registers

3.2.1 Register allocation
ARM DDI 0301H
ID012310
This section gives details of all the registers in the system control coprocessor. The section
presents a summary of the registers and detailed descriptions in register order of CRn,
Opcode_1, CRm, Opcode_2.
You can access CP15 registers with MRC and MCR instructions:
MCR{cond} P15,<Opcode_1>,<Rd>,<CRn>,<CRm>,<Opcode_2>
MRC{cond} P15,<Opcode_1>,<Rd>,<CRn>,<CRm>,<Opcode_2>
Table 3-2 on page 3-14 lists the allocation and reset values of the registers of the system control
coprocessor where:
• CRn is the register number within CP15
• Op1 is the Opcode_1 value for the register
• CRm is the operational register
• Op2 is the Opcode_2 value for the register.
• Type applies to the Secure, S, or the Non-secure, NS, world and is:
— B, registers banked in Secure and Non-secure worlds. If the registers are not banked
then they are common to both worlds or only accessible in one world.
— NA, no access
RO, read-only access
—
— RO, read-only access in privileged modes only
R/W, read/write access
—
— R/W, read/write access in privileged modes only
WO, write-only access
—
— WO, write-only access in privileged modes only
— X, access depends on another register or external signal.
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System Control Coprocessor
3-13