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Banked registers
Base register
Base register write-back
Beat
BE-8
BE-32
Big-endian
Big-endian memory
ARM DDI 0301H
ID012310
The following AXI terms are slave interface attributes. To obtain optimum performance, they
must be specified for all components with an AXI slave interface
Combined acceptance capability
The maximum number of active transactions that a slave interface can accept.
This is specified instead of write or read acceptance capability for slave interfaces
that use a combined storage for active write and read transactions.
Read acceptance capability
The maximum number of active read transactions that a slave interface can
accept.
Read data reordering depth
The number of active read transactions for which a slave interface can transmit
data. This is counted from the earliest transaction.
Write acceptance capability
The maximum number of active write transactions that a slave interface can
accept.
Write interleave depth
The number of active write transactions for which the slave interface can receive
data. This is counted from the earliest transaction.
Those physical registers whose use is defined by the current processor mode. The banked
registers are R8 to R14.
A register specified by a load or store instruction that is used to hold the base value for the
instruction's address calculation. Depending on the instruction and its addressing mode, an
offset can be added to or subtracted from the base register value to form the virtual address that
is sent to memory.
Updating the contents of the base register used in an instruction target address calculation so that
the modified address is changed to the next higher or lower sequential address in memory. This
means that it is not necessary to fetch the target address for successive instruction transfers and
enables faster burst accesses to sequential memory.
Alternative word for an individual transfer within a burst. For example, an INCR4 burst
comprises four beats.
See also Burst.
Big-endian view of memory in a byte-invariant system.
See also BE-32, LE, Byte-invariant and Word-invariant.
Big-endian view of memory in a word-invariant system.
See also BE-8, LE, Byte-invariant and Word-invariant.
Byte ordering scheme in which bytes of decreasing significance in a data word are stored at
increasing addresses in memory.
See also Little-endian and Endianness.
Memory in which:
- a byte or halfword at a word-aligned address is the most significant byte or halfword within
the word at that address
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