Table 3-23 Results Of Access To The Memory Model Feature Register 1 - ARM ARM1176JZF-S Technical Reference Manual

Field
Bits
name
[11:8] -
[7:4] -
[3:0] -
ARM DDI 0301H
ID012310
Table 3-22 Memory Model Feature Register 1 bit functions (continued)
Function
Indicates support for level one cache line maintenance operations by Set/Way, Harvard architecture.
, ARM1176JZF-S processors support:
0x3
• clean data cache line by Set/Way
• clean and invalidate data cache line by Set/Way
• invalidate data cache line by Set/Way
• invalidate instruction cache line by Set/Way.
Indicates support for level one cache line maintenance operations by MVA, unified architecture.
0, no support in ARM1176JZF-S processors.
Indicates support for level one cache line maintenance operations by MVA, Harvard architecture.
0x2 , ARM1176JZF-S processors support:
• clean data cache line by MVA
• invalidate data cache line by MVA
• invalidate instruction cache line by MVA
• clean and invalidate data cache line by MVA
• invalidation of branch target buffer by MVA.
Table 3-23 lists the results of attempted access for each mode.

Table 3-23 Results of access to the Memory Model Feature Register 1

Secure Privileged
Read Write
Data Undefined exception
To use the Memory Model Feature Register 1 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 5.
For example:
MRC p15, 0, <Rd>, c0, c1, 5 ;Read Memory Model Feature Register 1.
c0, Memory Model Feature Register 2
The purpose of the Memory Model Feature Register 2 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 2 is:
• in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-19 on page 3-34 shows the bit arrangement for Memory Model Feature Register 2.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Data Undefined exception
System Control Coprocessor
User
Undefined exception
3-33