Table of Contents
Advertisement
Field
Bits
name
[31:28]
-
[27:24]
-
[23:20]
-
[19:16]
-
[15:12]
-
ARM DDI 0301H
ID012310
To use the Memory Model Feature Register 0 read CP15 with:
•
Opcode_1 set to 0
•
CRn set to c0
•
CRm set to c1
•
Opcode_2 set to 4.
For example:
MRC p15, 0, <Rd>, c0, c1, 4 ;Read Memory Model Feature Register 0.
c0, Memory Model Feature Register 1
The purpose of the Memory Model Feature Register 1 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 1 is:
•
in CP15 c0
•
a 32-bit read-only register common to the Secure and Non-secure worlds
•
accessible in privileged modes only.
Figure 3-18 shows the bit arrangement for Memory Model Feature Register 1.
31
28 27
24 23
-
-
Table 3-22 lists how the bit values correspond with the Memory Model Feature Register 1
functions.
Function
Indicates support for branch target buffer.
, ARM1176JZF-S processors require flushing of branch predictor on VA change.
0x1
Indicates support for test and clean operations on data cache, Harvard or unified architecture.
0x0
, no support in ARM1176JZF-S processors.
Indicates support for level one cache, all maintenance operations, unified architecture.
, no support in ARM1176JZF-S processors.
0x0
Indicates support for level one cache, all maintenance operations, Harvard architecture.
0x3
, ARM1176JZF-S processors support:
•
invalidate instruction cache including branch prediction
•
invalidate data cache
•
invalidate instruction and data cache including branch prediction
•
clean data cache, recursive model using cache dirty status bit
•
clean and invalidate data cache, recursive model using cache dirty status bit.
Indicates support for level one cache line maintenance operations by Set/Way, unified architecture.
0x0
, no support in ARM1176JZF-S processors.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
20 19
16 15
-
-
-
Figure 3-18 Memory Model Feature Register 1 format
Table 3-22 Memory Model Feature Register 1 bit functions
System Control Coprocessor
12 11
8 7
4 3
-
-
0
-
3-32
Hide quick links:
Advertisement
Table of Contents
