Table 3-58 Results Of Access To The Translation Table Base Control Register - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 3-58 lists the results of attempted access for each mode.

Table 3-58 Results of access to the Translation Table Base Control Register

Secure Privileged
Read Write
Secure data Secure data
To use the Translation Table Base Control Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c2
• CRm set to c0
• Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c2, c0, 2
MCR p15, 0, <Rd>, c2, c0, 2
A translation table base register is selected like this:
• If N is set to 0, always use Translation Table Base Register 0. This is the default case at
reset. It is backwards compatible with ARMv5 and earlier processors.
• If N is set greater than 0, and bits [31:32-N] of the VA are all 0, use Translation Table Base
Register 0, otherwise use Translation Table Base Register 1. N must be in the range 0-7.
Note
The ARM1176JZF-S processor cannot page table walk from level one cache. Therefore, if C is
set to 1, to ensure coherency, you must either store page tables in Inner write-through memory
or, if in Inner write-back, you must clean the appropriate cache entries after modification so that
the mechanism for the hardware page table walks sees them.
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Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Non-secure data Non-secure data
; Read Translation Table Base Control Register
; Write Translation Table Base Control Register
System Control Coprocessor
User
Undefined exception
3-62