Power Control Register - ARM Cortex A9 Technical Reference Manual

4.3.22

Power Control Register

Bits Name
[31:11] -
[10:8] max_clk_latency
[7:1] -
[0] Enable dynamic
clock gating
ARM DDI 0388I
ID073015
The Power Control Register characteristics are:
Purpose Enables you to set:
•
•
Usage constraints •
•
Configurations Available in all configurations.
Attributes See the register summary in
Figure 4-21 shows the Power Control Register bit assignments.
31
Table 4-48 shows the Power Control Register bit assignments.
Function
Reserved.
Samples the value present on the MAXCLKLATENCY pins on exit from reset.
This value reflects an implementation-specific parameter. ARM strongly recommends that the
software does not modify it.
The max_clk_latency bits determine the length of the delay between when one of these blocks has its
clock cut and the time when it can receive new active signals.
If the value determined by max_clk_latency is lower than the real delay, the block that had its clock
cut can receive active signals even though it does not have a clock. This can cause the device to
malfunction.
If the value determined by max_clk_latency is higher than the real delay, the master block waits extra
cycles before sending its signals to the block that had its clock cut. This can have some performance
impact.
When the value is correctly set, the block that had its clock cut receives active signals on the first clock
edge of the wake-up. This gives optimum performance.
Reserved.
Disabled at reset.
To access the Power Control Register, read or write the CP15 register with:
MRC p15,0,<Rd>,c15,c0,0; Read Power Control Register
MCR p15,0,<Rd>,c15,c0,0; Write Power Control Register
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Non-Confidential
the clock latency for your implementation of the Cortex-A9
processor
dynamic clock gating.
a read/write register in Secure state
a read-only register in Non-secure state.
Table 4-15 on page
Reserved
max_clock_latency
Figure 4-21 Power Control Register bit assignments
Table 4-48 Power Control Register bit assignments
System Control
4-11.
11 10 8 7
Reserved
Enable dynamic clock gating
1 0
4-41