Table 3-37 Results Of Access To The Instruction Set Attributes Register 4; Table 3-38 Results Of Access To The Instruction Set Attributes Register 5 - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 3-37 lists the results of attempted access for each mode.

Table 3-37 Results of access to the Instruction Set Attributes Register 4

Secure Privileged
Read Write
Data Undefined exception
To use the Instruction Set Attributes Register 4 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c2
• Opcode_2 set to 4.
For example:
MRC p15, 0, <Rd>, c0, c2, 4 ;Read Instruction Set Attributes Register 4
c0, Instruction Set Attributes Register 5
The purpose of the Instruction Set Attributes Register 5 is to provide additional information
about the properties of the processor.
The Instruction Set Attributes Register 5 is:
• in CP15 c0
• a 32-bit read-only registers common to the Secure and Non-secure worlds
• accessible in privileged modes only.
The contents of the Instruction Set Attributes Register 5 are implementation defined. In the
ARM1176JZF-S processor, Instruction Set Attributes Register 5 is read as
Table 3-38 lists the results of attempted access for each mode.

Table 3-38 Results of access to the Instruction Set Attributes Register 5

Secure Privileged
Read Write
Data Undefined exception
To use the Instruction Set Attributes Register 5 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set toc2
• Opcode_2 set to 5.
For example:
MRC p15, 0, <Rd>, c0, c2, 5 ;Read Instruction Set Attribute Register 5.
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Non-Confidential, Unrestricted Access
System Control Coprocessor
Non-secure Privileged
Read Write
Data Undefined exception
Non-secure Privileged
Read Write
Data Undefined exception
User
Undefined exception
0x00000000 .
User
Undefined exception
3-43