ARM ARM1176JZF-S Technical Reference Manual page 757

Thumb state
Tightly coupled memory (TCM)
Tiny
TLB
Trace hardware
Trace port
Translation Lookaside Buffer (TLB)
Translation table
Translation table walk
Trap
Trigger instruction
Undefined
UNP
Unpredictable
Unsupported values
ARM DDI 0301H
ID012310
A processor that is executing Thumb (16-bit) halfword aligned instructions is operating in
Thumb state.
An area of low latency memory that provides predictable instruction execution or data load
timing in cases where deterministic performance is required. TCMs are suited to holding:
- critical routines (such as for interrupt handling)
- scratchpad data
- data types whose locality is not suited to caching
- critical data structures, such as interrupt stacks.
A nonzero result or value that is between the positive and negative minimum normal values for
the destination precision.
See Translation Look-aside Buffer.
A term for a device that contains an Embedded Trace Macrocell.
A port on a device, such as a processor or ASIC, used to output trace information.
A cache of recently used page table entries that avoid the overhead of page table walking on
every memory access. Part of the Memory Management Unit.
A table, held in memory, that contains data that defines the properties of memory areas of
various fixed sizes.
The process of doing a full translation table lookup. It is performed automatically by hardware.
An exceptional condition in a VFP coprocessor that has the respective exception enable bit set
in the FPSCR register. The user trap handler is executed.
The VFP coprocessor instruction that causes a bounce at the time it is issued. A potentially
exceptional instruction causes the VFP11 coprocessor to enter the exceptional state. A
subsequent instruction, unless it is an FMXR or FMRX instruction accessing the FPEXC,
FPINST, or FPSID register, causes a bounce, beginning exception processing. The trigger
instruction is not necessarily exceptional, and no processing of it is performed. It is retried at the
return from exception processing of the potentially exceptional instruction.
See also Bounce, Potentially exceptional instruction, and Exceptional state.
Indicates an instruction that generates an Undefined instruction trap. See the ARM Architecture
Reference Manual for more details on ARM exceptions.
See Unpredictable.
Unpredictable refers to Architecturally Unpredictable behavior. Unpredictable results of a
particular instruction or operation cannot be relied on. Unpredictable instructions or results do
not represent security holes and do not halt or hang the processor, or any parts of the system.
Specific data values that are not processed by the VFP coprocessor hardware but bounced to the
support code for completion. These data can include infinities, NaNs, subnormal values, and
zeros. An implementation is free to select which of these values is supported in hardware fully
or partially, or requires assistance from support code to complete the operation. Any exception
resulting from processing unsupported data is trapped to user code if the corresponding
exception enable bit for the exception is set.
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