Table of Contents
Advertisement
14.7.4
Transferring data between the host and the core
14.7.5
Using the debug communications channel
ARM DDI 0301H
ID012310
8.
5 into the SCREG.
9.
ITRsel into the IR. Now the DBGTAP controller works as if EXTEST and scan chain 4 is
selected.
10.
Scan the
MCR p14,0,R0,c0,c5,0
11.
Go through the Run-Test/Idle state of the DBGTAPSM.
12.
INTEST into the IR. Now INTEST and scan chain 5 are selected.
13.
Scan out 34 bits. The 33rd bit indicates if the instruction has completed. If the bit is clear,
repeat this step again.
14.
The least significant 32 bits hold the contents of R0.
The number of steps has been reduced from 16 to 14. However, the bigger reduction comes
when reading additional registers. Using the ITRsel instruction there are 6 extra steps, 9 to 14,
compared with 10 extra steps, 7 to 16, in the first sequence.
There are two ways that a DBGTAP debugger can send or receive data from the core:
•
using the DCC, when the processor is not in Debug state
•
using the instruction execution mechanism that Executing instructions in Debug state on
page 14-21 describes, when the core is in Debug state.
The following sections describe this:
•
Using the debug communications channel.
•
Target to host debug communications channel sequence on page 14-24
•
Host to target debug communications channel on page 14-24
•
Transferring data in Debug state on page 14-25
•
Example sequences on page 14-26.
The DCC is defined as the set of resources that the external DBGTAP debugger uses to
communicate with a piece of software running on the core.
The DCC in the processor is implemented using the two physically separate DTRs and a
full/empty bit pair to augment each register, creating a bidirectional data port. One register can
be read from the DBGTAP and is written from the processor. The other register is written from
the DBGTAP and read by the processor. The full/empty bit pair for each register is automatically
updated by the debug unit hardware, and is accessible to both the DBGTAP and to software
running on the processor.
At the core side, the DCC resources are the following:
•
CP14 debug register c5, DTR. Data coming from a DBGTAP debugger can be read by an
MRC or STC instruction addressed to this register. The core can write to this register any
data intended for the DBGTAP debugger, using an MCR or LDC instruction. Because the
DTR comprises both a read, rDTR, and a write portion, wDTR, a piece of data written by
the core and another coming from the DBGTAP debugger can be held in this register at
the same time.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
instruction into the ITR.
Debug Test Access Port
14-23
Hide quick links:
Advertisement
Table of Contents
