Table 13-8 Processor Breakpoint And Watchpoint Registers - ARM ARM1176JZF-S Technical Reference Manual

VCR bit
VCR[30] = 1
VCR[31] = 1
13.3.7 CP14 c64-c69, Breakpoint Value Registers (BVR)
Binary address
Opcode_2
b100
ARM DDI 0301H
ID012310
Table 13-7 Summary of debug entry and exception conditions (continued)
NS bit, mode
NS bit = 1 and mode ≠ Secure
Monitor
NS bit = 1 and mode ≠ Secure
Monitor
Table 13-8 lists the Breakpoint Value Registers that the processor implements.
Register
number
CRm
b0000-b0011 c64-c67
b0100-b0101 c68-c69
Each BVR is associated with a BCR register. BCRy is the corresponding control register for
BVRy.
A pair of breakpoint registers, BVRy/BCRy, is called a Breakpoint Register Pair (BRP).
BVR0-5 are paired with BCR0-5 to make BRP0-5.
The BVR of a BRP is loaded with an IMVA and then its contents can be compared against the
IMVA bus of the processor. The breakpoint value contained in the BVR corresponds to either
an IMVA or a context ID. Breakpoints can be set on:
• an IMVA
• a context ID
• an IMVA/context ID pair.
The IMVA comparison can be programmed to either hit when the address matches or
mis-matches. The IMVA mis-match case is useful because it enables a debugger to implement
a single-step operation when the breakpoint is programmed to match any other IMVA than the
instruction about to be executed.
The processor supports thread-aware breakpoints and watchpoints. A context ID can be loaded
into the BVR and the BCR can be configured so this BVR value is compared against the CP15
Context ID Register, c13, instead of the IMVA bus. Another register pair loaded with an IMVA
or DMVA can then be linked with the context ID holding BRP. A breakpoint or watchpoint
debug event is only generated if both the address and the context ID match at the same time.
This means that unnecessary hits can be avoided when debugging a specific thread within a task.
Breakpoint debug events generated on context ID matches only are also supported. However, if
a context ID only match or any match including an IMVA mis-match occurs while the processor
is running in a privileged mode and the debug logic in Monitor debug-mode, it is ignored. This
is to avoid the processor ending in an unrecoverable state.
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VE HIVECS
0 0
1
1 X
X 0
1

Table 13-8 Processor breakpoint and watchpoint registers

CP14 debug register name
Breakpoint Value Registers 0-3
Breakpoint Value Registers 4-5
Prefetch vector
NSBA +
0x00000018
0xFFFF0018
Most recent Non-secure IRQ address.
NSBA +
0x0000001C
0xFFFF001C
Context ID
Abbreviation
capable?
BVR0-3 No
BVR4-5 Yes
Debug
13-16