Table 4-5 Mixed-Endian Configuration; Table 4-6 B Bit, U Bit, And Ee Bit Settings - ARM ARM1176JZF-S Technical Reference Manual

U B E
1 0 0
1 0 1
1 1 0
1 1 1
4.5.3 Reset values of the U, B, and EE bits
ARM DDI 0301H
ID012310
Mixed-endian configuration supported
This behavior is enabled when the U bit in CP15 Register c1 is set. This is only supported when
the B bit in CP15 Register c1 is reset, as Table 4-5 lists.
Instruction Data
endianness endianness
LE LE
LE BE-8
BE-32 BE-32
- -
Table 4-6 lists the reset values of the BIGENDINIT and UBITINIT pins that determine the
values of the U, B, and EE bits at reset. The pins determine the reset value of the B bit and both
the Secure and Non-secure reset values of the U and EE bits.
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Unaligned and Mixed-endian Data Access Support

Table 4-5 Mixed-endian configuration

Description
LE instructions, little-endian data load/store. Unaligned data access
permitted.
LE instructions, big-endian data load/store. Unaligned data access
permitted.
Legacy BE instructions/data.
Reserved.

Table 4-6 B bit, U bit, and EE bit settings

BIGENDINIT
0
0
1
1
UBITINIT B U EE
0 0 0 0
1 0 1 0
0 1 0 0
1 0 1 1
4-19