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11.2
Coprocessor pipeline
11.2.1
Coprocessor instructions
Instruction
CDP
MRC
MCR
MRRC
MCRR
STC
LDC
ARM DDI 0301H
ID012310
The coprocessor interface achieves loose synchronization between the two pipelines by
exchanging tokens from one pipeline to the other. These tokens pass down queues between the
pipelines and can carry additional information. In most cases the primary purpose of the queue
is to carry information about the instruction being processed, or to inform one pipeline of events
occurring in the other.
Tokens are generated whenever a coprocessor instruction passes out of a pipeline stage
associated with a queue into the next stage. These tokens are picked up by the partner stage in
the other pipeline, and used to enable the corresponding instruction in that stage to move on. The
movement of coprocessor instructions down each pipeline is matched exactly by the movement
of tokens along the various queues that connect the pipelines.
If a pipeline stage has no associated queue, the instruction contained within it moves on in the
normal way. The coprocessor interface is data-driven rather than control-driven.
Each coprocessor might only execute a subset of all possible coprocessor instructions.
Coprocessors reject those instructions they cannot handle. Table 11-1 lists all the coprocessor
instructions supported by the processor and gives a brief description of each. For more details
of coprocessor instructions, see the ARM Architecture Reference Manual.
Data transfer
Vectored
None
No
Store
No
Load
No
Store
No
Load
No
Store
Yes
Load
Yes
The coprocessor instructions fall into three groups:
•
loads
•
stores
•
processing instructions.
The load and store instructions enable information to pass between the core and the coprocessor.
Some of them might be vectored. This enables several values to be transferred in a single
instruction. This typically involves the transfer of several words of data between a set of registers
in the coprocessor and a contiguous set of locations in memory.
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Description
Processes information already held within the coprocessor
Transfers information from the coprocessor to the core registers
Transfers information from the core registers to the coprocessor
Transfers information from the coprocessor to a pair of registers in the
core
Transfers information from a pair of registers in the core to the
coprocessor
Transfers information from the coprocessor to memory and might be
iterated to transfer a vector
Transfers information from memory to the coprocessor and might be
iterated to transfer a vector
Coprocessor Interface
Table 11-1 Coprocessor instructions
11-3
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