ARM ARM1176JZF-S Technical Reference Manual page 759

Write completion
Write-through (WT)
WT
Cache terminology diagram
ARM DDI 0301H
ID012310
The memory system indicates to the processor that a write has been completed at a point in the
transaction where the memory system is able to guarantee that the effect of the write is visible
to all processors in the system. This is not the case if the write is associated with a memory
synchronization primitive, or is to a Device or Strongly Ordered region. In these cases the
memory system might only indicate completion of the write when the access has affected the
state of the target, unless it is impossible to distinguish between having the effect of the write
visible and having the state of target updated.
This stricter requirement for some types of memory ensures that any side-effects of the memory
access can be guaranteed by the processor to have taken place. You can use this to prevent the
starting of a subsequent operation in the program order until the side-effects are visible.
In a write-through cache, data is written to main memory at the same time as the cache is
updated.
See Write-through.
The following diagram illustrates the following cache terminology:
• block address
• cache line
• cache set
• cache way
• index
• tag.
Block address
Tag Index
Line number
Tag
Tag
Cache tag RAM
=
Hit
(way number)
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Word Byte
Cache way Cache set
0
1
2
Tag 3
Tag
4
5 m
6
7
3
n 2
1
0
(way that corresponds)
Cache line
Word number
2
1 0
Cache data RAM
Read data
Glossary
Glossary-20