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7.3
Tightly-coupled memory
ARM DDI 0301H
ID012310
The TCM is designed to provide low-latency memory that can be used by the processor without
the unpredictability that is a feature of caches.
You can use such memory to hold critical routines, such as interrupt handling routines or
real-time tasks where the indeterminacy of a cache is highly undesirable. In addition you can
use it to hold scratch pad data, data types whose locality properties are not well suited to
caching, and critical data structures such as interrupt stacks.
You can separately configure the size of the Instruction TCM (ITCM) and the size of the Data
TCM (DTCM) to be 0KB, 4KB. 8KB, 16KB, 32KB or 64KB. For each side, ITCM and DTCM:
•
If you configure the TCM size to be 4KB you get one TCM, of 4KB, on this side.
•
If you configure the TCM size to be larger than 4KB you get two TCMs on this side, each
of half the configured size. So, for example, if you configure an ITCM size of 16KB you
get two ITCMs, each of size 8KB.
Table 7-1 lists all possible TCM configurations:
When the number of TCM on one side is 2, to make the implementation easier, the TCM for this
side are implemented as one single RAM. This RAM then has a size in the 0-64 KB range. The
lower part of the RAM corresponds to the TCM called TCM0 and the upper part corresponds to
TCM1.
You can also configure each individual TCM to contain Secure or Non-secure data. You make
this configuration in CP15 register c9, accessible in Secure state only. See c9, Data TCM
Non-secure Control Access Register on page 3-93 and c9, Instruction TCM Non-secure Control
Access Register on page 3-94 for more information. After reset, all TCMs are configured as
Secure.
The TCM Status Register in CP15 c0 describes what TCM options and TCM sizes can be
implemented, see c0, TCM Status Register on page 3-24.
Each Data TCM is implemented in parallel with the Data Cache and each Instruction TCM is
implemented in parallel with the Instruction Cache. Each TCM has a single movable base
address, specified in CP15 register c9, see c9, Data TCM Region Register on page 3-89 and c9,
Instruction TCM Region Register on page 3-91.
The size of each TCM can differ from the size of a cache way, but forms a single contiguous
area of memory. Figure 7-1 on page 7-4 shows the entire level one memory system. To access
each of the TCM region and TCM Access Control registers, the TCM Selection registers are set
to the TCM of interest, see c9, TCM Selection Register on page 3-96.
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Configured TCM size
Number of TCMs
0KB
0
4KB
1
8KB
2
16KB
2
32KB
2
64KB
2
Level One Memory System
Table 7-1 TCM configurations
Size of each TCM
0
4KB
4KB
8KB
16KB
32KB
7-7
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