Table 3-18 Auxiliary Feature Register 0 Bit Functions; Table 3-19 Results Of Access To The Auxiliary Feature Register 0 - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c0, c1, 2 ;Read Debug Feature Register 0
c0, Auxiliary Feature Register 0
The purpose of the Auxiliary Feature Register 0 is to provide additional information about the
features of the processor.
The Auxiliary Feature Register 0 is:
• in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Table 3-18 lists how the bit values correspond with the Auxiliary Feature Register 0 functions.
The contents of the Auxiliary Feature Register 0 [31:16] are Reserved. The contents of the
Auxiliary Feature Register 0 [15:0] are Implementation Defined. In the ARM1176JZF-S
processor, the Auxiliary Feature Register 0 reads as
Table 3-19 lists the results of attempted access for each mode.
Secure Privileged
Read Write
Data Undefined exception
To use the Auxiliary Feature Register 0 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 3.
For example:
MRC p15, 0, <Rd>, c0, c1, 3 ;Read Auxiliary Feature Register 0.
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Table 3-18 Auxiliary Feature Register 0 bit functions

Bits
[31:16]
[15:12]
[11:8]
[7:4]
[3:0]
0x00000000

Table 3-19 Results of access to the Auxiliary Feature Register 0

Non-secure Privileged
Read Write
Data Undefined exception
System Control Coprocessor
Field name Function
- Reserved. RAZ.
- Implementation Defined.
- Implementation Defined.
- Implementation Defined.
- Implementation Defined.
.
User
Undefined exception
3-30