ARM Cortex-M3 Technical Reference Manual
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ARM Cortex-M3 Technical Reference Manual

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Cortex-M3
™
Revision: r0p0
Technical Reference Manual
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B

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  • Page 1 Cortex-M3 ™ Revision: r0p0 Technical Reference Manual Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    Privileged access and User access ............2-3 Registers ..................... 2-4 Data types ....................2-10 Memory formats ..................2-11 Instruction set .................... 2-13 Chapter 3 System Control Summary of processor registers ..............3-2 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 4 MPU access permissions ................. 9-14 MPU aborts ....................9-16 Updating an MPU region ................9-17 Interrupts and updating the MPU .............. 9-20 Chapter 10 Core Debug 10.1 About core debug ..................10-2 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 5 Trace output ....................15-9 15.5 ETM architecture ..................15-10 15.6 ETM programmer’s model ............... 15-14 Chapter 16 Embedded Trace Macrocell Interface 16.1 About the ETM interface ................16-2 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 6 System bus interface .................. A-9 Private Peripheral Bus interface ............... A-10 ITM interface ..................... A-11 A.10 AHB-AP interface ..................A-12 A.11 ETM interface ................... A-13 A.12 Test interface .................... A-15 Glossary Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 7 Table 4-2 Memory region permissions ..................4-4 Table 4-3 Cortex-M3 ROM table ....................4-8 Table 5-1 Exception types ......................5-3 Table 5-2 Priority-based actions of exceptions ................. 5-5 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 8 Table 8-27 Bit functions of the Bus Fault Address Register ............. 8-37 Table 8-28 Software Trigger Interrupt Register bit assignments ..........8-38 Table 9-1 MPU registers ......................9-3 viii Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 9 Bit functions of the AHB-AP Data Read/Write Register ........11-41 Table 11-31 Bit functions of the AHB-AP Banked Data Register ..........11-41 Table 11-32 Bit functions of the AHB-AP Debug ROM Address Register ......... 11-42 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 10 Abort Register bit assignments ................12-50 Table 12-16 Identification Code Register bit assignments ............12-52 Table 12-17 JEDEC JEP-106 manufacturer ID code, with ARM Limited values ...... 12-53 Table 12-18 Control/Status Register bit assignments ............... 12-54 Table 12-19 Control of pushed operation comparisons by MASKLANE ........12-56 Table 12-20 Transfer Mode, TRNMODE, bit definitions ............
  • Page 11 Private Peripheral Bus interface ................A-10 Table A-9 ITM interface ......................A-11 Table A-10 AHB-AP interface ....................A-12 Table A-11 ETM interface ......................A-13 Table A-12 Test interface ......................A-15 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 12 List of Tables Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 13 Internal reset synchronization ................... 6-7 Figure 7-1 SLEEPING power control example ................7-4 Figure 7-2 SLEEPDEEP power control example ................ 7-5 Figure 8-1 Interrupt Controller Type Register bit assignments ........... 8-7 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. xiii...
  • Page 14 ITM Integration Mode Control bit assignments ............. 11-35 Figure 11-18 ITM Lock Status Register bit assignments ............11-36 Figure 11-19 AHB-AP Control and Status Word Register ............11-38 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 15 Unconditional branch without pipeline stalls ............16-6 Figure 16-6 Unconditional branch with pipeline stalls ............... 16-7 Figure 16-7 Unconditional branch in execute aligned ..............16-7 Figure 16-8 Unconditional branch in execute unaligned ............16-7 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 16 List of Figures Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 17 Preface This preface introduces the Cortex-M3 r0p0 Technical Reference Manual. It contains the following sections: • About this manual on page xviii • Feedback on page xxiii. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. xvii...

  • Page 18: Preface

    Read this chapter to learn about the components of the Cortex-M3 processor, and about the processor instruction set. Chapter 2 Programmer’s Model Read this chapter to learn about the Cortex-M3 register set, modes of operation, and other information for programming the Cortex-M3 processor.
  • Page 19 Chapter 17 Instruction Timing Read this chapter to learn about the processor instruction timing and clock cycles. Appendix A Signal Descriptions Read this appendix for a summary of Cortex-M3 signals. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 20 The figure named Key to timing diagram conventions on page xxi explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 21: Key To Timing Diagram Conventions

    'o7654 is an unsized octal value. • 8'd9 is an eight-bit wide decimal value of 9. • 8'h3F is an eight-bit wide hexadecimal value of . This is 0x3F equivalent to b00111111. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 22 ARM Limited http://www.arm.com Frequently Asked Questions list. ARM publications This manual contains information that is specific to the Cortex-M3 processor. See the following documents for other relevant information: • ARM Architecture Reference Manual (ARM DDI 0100) •...

  • Page 23: Feedback

    Preface Feedback ARM Limited welcomes feedback both on the Cortex-M3 processor, and on the documentation. Feedback on the Cortex-M3 processor If you have any comments or suggestions about this product, please contact your supplier giving: • the product name •...
  • Page 24 Preface xxiv Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 25 • About the processor on page 1-2 • Components of the processor on page 1-4 • Configurable options on page 1-12 • Instruction set summary on page 1-13. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 26: Chapter 1 Introduction

    The processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require fast interrupt response features. The processor implements the ARM architecture v7-M. The processor incorporates: •...
  • Page 27 Low-cost debug solution that features: — Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset. — Serial Wire (SW-DP) or JTAG (JTAG-DP) debug access, or both.

  • Page 28: Components Of The Processor

    ITM on page 1-10 • MPU on page 1-10 • ETM on page 1-10 • TPIU on page 1-10. Figure 1-1 on page 1-5 shows the structure of the Cortex-M3. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 29: Figure 1-1 Cortex-M3 Block Diagram

    The processor components exist in two levels of hierarchy, as shown in Figure 1-1. This represents the RTL hierarchy of the design. Four components, ETM, TPIU, SW/JTAG-DP, and ROM table, are shown outside the Cortex-M3 level because these components are either optional, or there is flexibility in how they are implemented and used.
  • Page 30 TPIU. • In a production device, the TPIU might have been removed. Note There is no Cortex-M3 trace capability if the TPIU has been removed. SW/JTAG-DP The implementation options for the SW/JTAG-DP are: • Your implementation might contain either or both SW-DP and JTAG-DP.
  • Page 31 Registers The processor contains: • 13 general purpose 32-bit registers • Link Register (LR) • Program Counter (PC) • Program Status Register, xPSR • two banked SP registers. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 32 32-bit AHBLite bus. • System bus. This is for instruction and vector fetches, data load/stores and debug accesses to system space. This is a 32-bit AHBLite bus. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 33 • It contains several counters for performance profiling. • It can be configured to emit PC samples at defined intervals, and to emit interrupt event information. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 34 1.2.10 TPIU The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and ETM if present, and an off-chip Trace Port Analyzer. The TPIU can be configured to support either serial pin trace for low cost debug, or multi pin trace for higher bandwidth trace.
  • Page 35 The debug port provides debug access to all registers and memory in the system, including the processor registers. Chapter 12 Debug Port describes the SW/JTAG-DP in detail. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 1-11...

  • Page 36: Configurable Options

    The number of bits of interrupt priority can be configured at implementation from three to eight bits. 1.3.2 The Cortex-M3 system can be configured at implementation to include an MPU. Chapter 9 Memory Protection Unit describes the MPU. 1.3.3 The Cortex-M3 system can be configured at implementation to include an ETM.

  • Page 37: Instruction Set Summary

    CBNZ <Rn>,<label> Compare zero and branch CBZ <Rn>,<label> Compare negation of register value with another register value CMN <Rn>, <Rm> Compare immediate 8-bit value CMP <Rn>, #<immed_8> ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 1-13...
  • Page 38 MOV <Rd>, #<immed_8> Move low register value to low register MOV <Rd>, <Rn> Move high or low register value to high or low register MOV <Rd>, <Rm> 1-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 39 Store register halfword [15:0] to register address + register offset STRH <Rd>, [<Rn>, <Rm>] Subtract immediate 3-bit value from register SUB <Rd>, <Rn>, #<immed_3> Subtract immediate 8-bit value from register value SUB <Rd>, #<immed_8> ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 1-15...

  • Page 40: Table 1-2 32-Bit Cortex-M3 Instruction Summary

    ASR{S}.W <Rd>, <Rn>, <Rm> Conditional branch B{cond}.W <label> Clear bit field BFC.W <Rd>, #<lsb>, #<width> Insert bit field from one register value into another BFI.W <Rd>, <Rn>, #<lsb>, #<width> 1-16 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 41 Memory word to PC from base register address immediate LDR.W PC, #<+/-<offset_8> 8-bit offset, postindexed Memory word from base register address immediate 8-bit LDR.W <Rxf>, [<Rn>], #+/–<offset_8> offset, postindexed ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 1-17...
  • Page 42 LDRH.W <Rxf>. [<Rn>], #+/-<offset_8> 8-bit offset, postindexed Memory halfword [15:0] from register address shifted left by LDRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}] 0, 1, 2, or 3 places 1-18 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 43 Move immediate 12-bit value to register MOV{S}.W <Rd>, #<modify_constant(immed_12)> Move shifted register value to register MOV{S}.W <Rd>, <Rm>{, <shift>} Move immediate 16-bit value to top halfword [31:16] of MOVT.W <Rd>, #<immed_16> register ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 1-19...
  • Page 44 Multiply signed halfwords and add signed-extended value to SMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm> 2-register value Multiply two signed register values SMULL.W <RdLo>, <RdHi>, <Rn>, <Rm> Signed saturate SSAT <c> <Rd>, #<imm>, <Rn>{, <shift>} 1-20 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 45 Subtract shifted register value from register value SUB{S}.W <Rd>, <Rn>, <Rm>{, <shift>} Subtract immediate 12-bit value from register value SUBW.W <Rd>, <Rn>, #<immed_12> Sign extend byte to 32 bits SXTB.W <Rd>, <Rm>{, <rotation>} ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 1-21...
  • Page 46 Copy unsigned byte to register and zero-extend to 32 bits UXTB.W <Rd>, <Rm>{, <rotation>} Copy unsigned halfword to register and zero-extend to 32 bits UXTH.W <Rd>, <Rm>{, <rotation>} Wait for event WFE.W Wait for interrupt WFI.W 1-22 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 47 Privileged access and User access on page 2-3 • Registers on page 2-4 • Data types on page 2-10 • Memory formats on page 2-11 • Instruction set on page 2-13. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 48: Chapter 2 Programmer's Model

    Thumb instruction set and the base Thumb-2 32-bit instruction set architecture. The processor cannot execute ARM instructions. The Thumb instruction set is a subset of the ARM instruction set, re-encoded to 16 bits. It supports higher code density and systems with memory data buses that are 16 bits wide or narrower.

  • Page 49: Privileged Access And User Access

    It is also possible to switch from Main Stack to Process Stack while in Thread Mode by writing to CONTROL[1] using the MSR instruction, as well as being selectable using the EXC_RETURN value from an exit from Handler Mode. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 50: Registers

    Programmer’s Model Registers The Cortex-M3 processor has the following 32-bit registers: • 13 general-purpose registers, r0-r12 • stack point alias of banked registers, SP_process and SP_main • link register, r14 • program counter, r15 • one program status register, xPSR.

  • Page 51: Figure 2-2 Application Program Status Register Bit Assignments

    Application PSR The Application PSR (APSR) contains the condition code flags. Before entering an exception, the Cortex-M3 processor saves the condition code flags on the stack. You can access the APSR with the MSR(2) and MRS(2) instructions. Figure 2-2 shows the fields of the APSR.

  • Page 52: Table 2-1 Application Program Status Register Bit Assignments

    The Interrupt PSR (IPSR) contains the ISR number of the current exception activation. Figure 2-2 on page 2-5 shows the fields of the IPSR. Figure 2-3 Interrupt Program Status Register bit assignments Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 53: Table 2-2 Interrupt Program Status Register Bit Assignments

    The ICI field of the EPSR holds the information required to continue the load or store multiple from the point at which the interrupt occurred. If-then state field The IT field of the EPSR contain the execution state bits for the If-Then instruction. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 54: Table 2-3 Bit Functions Of The Execution Psr

    PC is 0. It can also be cleared by unstacking from an exception where the stacked T bit is 0. Executing an instruction while the T bit is clear causes an INVSTATE exception. [23:16] Reserved. [9:0] Reserved. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 55 If an LDM has completed a base load, it is continued from before the base load. Saved x PSR bits On entering an exception, the processor saves the combined information from the three status registers on the stack. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 56: Data Types

    8-bit bytes. Note Memory systems are expected to support all data types. In particular, the system must support subword writes without corrupting neighboring bytes in that word. 2-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 57: Memory Formats

    It always accesses code in little-endian format. Note Little-endian is the default memory format for ARM processors. In little-endian format, the byte with the lowest address in a word is the least-significant byte of the word. The byte with the highest address in a word is the most significant.

  • Page 58: Figure 2-5 Little-Endian And Big-Endian Memory Formats

    Word at address 0 address 3 address 2 address 1 address 0 Halfword 0 at address 2 Halfword 1 at address 0 Figure 2-5 Little-endian and big-endian memory formats 2-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 59: Instruction Set

    Programmer’s Model Instruction set The Cortex-M3 processor does not support ARM instructions. The Cortex-M3 processor supports all ARMv6 Thumb instructions except those listed in Table 2-4. Table 2-4 Nonsupported Thumb instructions Instruction Action if executed BLX(1) Branch with link and exchange BLX(1) always faults.
  • Page 60 STC), and YIELD (hinted NOP). Note, no MRS(1), MSR(1), or SUBS (PC return link). Combined branch CBZ and CBNZ (Compare and Branch if register is Zero or Non-Zero). Extended IT and NOP. This includes YIELD. 2-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 61 Set the xPSR Q bit if so, saturate the value if overflow detected. Saturation refers to the largest unsigned value or the largest/smallest signed value for the size selected. Note All coprocessor instructions generate a NOCP fault. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 2-15...
  • Page 62 Programmer’s Model 2-16 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 63: Chapter 3 System Control

    Chapter 3 System Control This chapter lists the registers that are used to program the Cortex-M3 system. It contains the following section: • Summary of processor registers on page 3-2. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 64: Summary Of Processor Registers

    Irq 0 to 31 Set Enable Register Read/write 0x00000000 0xE000E11C Irq 224 to 239 Set Enable Register Read/write 0x00000000 0xE000E180 Irq 0 to 31 Clear Enable Register Read/write 0x00000000 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 65 Irq 0 to 31 Priority Register Read/write 0x00000000 0xE000E4F0 0x00000000 Irq 236 to 239 Priority Register Read/write 0xE000ED00 0x410FC230 CPUID Base Register Read-only 0xE000ED04 Interrupt Control State Register Read/write 0x00000000 or read-only ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 66 ISAR0: ISA Feature register0 Read-only 0xE000ED60 0x01141110 ISAR1: ISA Feature register1 Read-only 0xE000ED64 0x02111000 ISAR2: ISA Feature register2 Read-only 0xE000ED68 0x21112231 ISAR3: ISA Feature register3 Read-only 0xE000ED6C 0x01111110 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 67 Debug Halting Control and Status Register Read/Write 0xE000EDF0 0x00000000 Debug Core Register Selector Register Write-only 0xE000EDF4 Debug Core Register Data Register Read/Write 0xE000EDF8 Debug Exception and Monitor Control Register. Read/Write 0xE000EDFC 0x00000000 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 68: Table 3-3 Flash Patch Register Summary

    Read-only Value 0x04 0xE0002FD4 PERIPID5 Read-only Value 0x00 0xE0002FD8 PERIPID6 Read-only Value 0x00 0xE0002FDC PERIPID7 Read-only Value 0x00 PERIPID0 Read-only 0xE0002FE0 Value 0x03 0xE0002FE4 PERIPID1 Read-only Value 0xB0 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 69: Table 3-4 Dwt Register Summary

    DWT Comparator Register DWT_MASK0 Read/write DWT Mask Registers 0xE0001024 DWT_FUNCTION0 Read/write DWT Function Registers 0xE0001028 0x00000000 DWT_COMP1 Read/write DWT Comparator Register 0xE0001030 DWT_MASK1 Read/write DWT Mask Registers 0xE0001034 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 70 PERIPHID3 Read-only Value 0x00 0xE0001FF0 0x0D PCELLID0 Read-only Value 0x0D PCELLID1 Read-only 0xE0001FF4 0xE0 Value 0xE0 0xE0001FF8 0x05 PCELLID2 Read-only Value 0x05 0xE0001FFC 0xB1 PCELLID3 Read-only Value 0xB1 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 71: Table 3-5 Itm Register Summary

    0xE0000FE4 0x000000B0 PERIPHID1 Read-only PERIPHID2 Read-only 0xE0000FE8 0x0000000B PERIPHID3 Read-only 0xE0000FEC 0x00000000 0xE0000FF0 0x0000000D PCELLID0 Read-only 0xE0000FF4 0x000000E0 PCELLID1 Read-only 0xE0000FF8 0x00000005 PCELLID2 Read-only 0xE0000FFC 0x000000B1 PCELLID3 Read-only ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 72: Table 3-6 Ahb-Ap Register Summary

    AHB-AP Banked Data Registers 0x1C (BD3) Debug ROM Read only 0xF8 0xE000E000 AHB-AP Debug ROM Address Register Address Identification Read only AHB-AP ID Register 0xFC 0x04770011 Register (IDR) 3-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 73: Table 3-7 Summary Of Debug Port Registers

    MPU Alias 1 Region Base Address register Alias of 0xE000EDA8 MPU Alias 1 Region Attribute and Size register Alias of 0xE000EDAC MPU Alias 2 Region Base Address register Alias of ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 3-11...

  • Page 74: Table 3-9 Tpiu Registers

    0xE0040304 Formatter and Flush Control Register Read-only 0x00 or 0x102 0xE0040308 Formatter Synchronization Counter Register Read-only 0x00 0xE0040EF0 Integration Register: ITATBCTR2 Read-only 0xE0040EF8 Integration Register: ITATBCTR0 Read-only 3-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 75: Table 3-10 Etm Registers

    CID Comparators Write-only 0xE00411B0-0xE00411BC Implementation specific Write-only 0xE00411C0-0xE00411DC 0xE00411E0 Synchronization Frequency Write-only ETM ID Read-only 0xE00411E4 0xE00411E8 Configuration Code Extension Read-only 0xE00411EC Extended External Input Selector Write-only ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 3-13...
  • Page 76 Peripheral ID 2 Read-only 0xE0041FEC Peripheral ID 3 Read-only 0xE0041FF0 Component ID 0 Read-only 0xE0041FF4 Component ID 1 Read-only 0xE0041FF8 Component ID 2 Read-only 0xE0041FFC Component ID 3 Read-only 3-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 77 This chapter describes the processor fixed memory map and its bit-banding feature. It contains the following sections: • About the memory map on page 4-2 • Bit-banding on page 4-5 • ROM memory table on page 4-8. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 78: Chapter 4 Memory Map

    Memory Map About the memory map Figure 4-1 shows the fixed Cortex-M3 memory map. Figure 4-1 The Cortex-M3 Memory Map Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 79: Table 4-1 Memory Interfaces

    Device type Cache Code Normal 0x00000000-0x1FFFFFFF SRAM Normal WBWA 0x20000000-0x3FFFFFFF SRAM_bitband 0x22000000-0x23FFFFFF Internal Peripheral 0x40000000-0x5FFFFFFF Device Periph_bit band Internal 0x42000000-0x43FFFFFF External RAM Normal WBWA 0x60000000-0x7FFFFFFF External RAM Normal 0x80000000-0x9FFFFFFF ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 80 0xE0100000 - 0xFFFFFFFF XN. This cannot be overridden by the Memory Protection Unit (MPU). For a description of the processor bus interfaces, see Chapter 14 Bus Interface. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 81: Bit-Banding

    1MB of the SRAM and Peripheral memory regions respectively. These bit-band regions map each word in an alias region of memory to a bit in a bit-band region of memory. The Cortex-M3 memory map has two 32-MB alias regions that map to two 1-MB bit-band regions: •...

  • Page 82: Figure 4-2 Bit-Band Mapping

    0x00 targeted bit is clear. Bits [31:1] will be zero. Note Big endian accesses to the bit-band alias region must be byte-sized. Otherwise, the accesses are unpredictable. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 83 Memory Map 4.2.2 Directly accessing a bit-band region The bit-band region can be directly accessed with normal reads and writes and writes to that region. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 84: Rom Memory Table

    MEMTYPE field has bit 0 defined for “System memory access” if 1, debug only if 0. 0xFD0 PID4 0xFD4 PID5 0xFD8 PID6 0xFDC PID7 0xFE0 PID0 0xFE4 PID1 0xFE8 PID2 0xFEC PID3 0xFF0 CID0 0x0D Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 85 Memory Map Table 4-3 Cortex-M3 ROM table Offset Value Name Description 0xFF4 CID1 0x10 0xFF8 CID2 0x05 0xFFC CID3 0xB1 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 86 Memory Map 4-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 87 Exception control transfer on page 5-23 • Setting up multiple stacks on page 5-24 • Abort model on page 5-26 • Activation levels on page 5-31 • Flowcharts on page 5-33. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 88: Chapter 5 Exceptions

    ISRs. • Dynamic reprioritization of interrupts. • Closely-coupled interface between the Cortex-M3 core and the NVIC to enable early processing of interrupts and processing of late-arriving interrupts with higher priority. • Configurable number of interrupts, from 1 to 240.

  • Page 89: Exception Types

    Usage fault, such as Undefined instruction executed or illegal state transition attempt. This is synchronous. 7-10 Reserved SVCall settable System service call with SVC instruction. This is synchronous. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 90 NVIC priority value of 0 to N, where N is the largest priority value implemented. Internally, the highest user-settable priority (0) is treated as 4. b. You can enable or disable this fault. See System Handler Control and State Register bit assignments on page 8-28. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 91: Exception Priority

    In the processor exception model, priority determines when and how the processor takes exceptions. You can: • assign software priority levels to interrupts • group priorities by splitting priority levels into pre-emption priorities and subpriorities. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 92 Where two pending exceptions have the same priority, the lower pending exception number has priority over the higher pending exception number. This is consistent with the priority precedence scheme. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 93: Table 5-3 Priority Grouping

    An interrupt can preempt another interrupt in progress only if its pre-emption priority is higher than that of the interrupt in progress. For more information on priority optimizations, Priority Level grouping, and Priority masking, see the ARMv7-M Architecture Reference Manual. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 94: Privilege And Stacks

    For a basic protected thread model, the user threads run in Thread mode using the Process stack, and the kernel and the interrupts run privileged using the Main stack. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 95 Access rules to memory locations based on an MPU. When fitted with an MPU, the access restrictions can control what memory can be read, written, and executed. Only Thread mode can be unprivileged. All exceptions are privileged. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 96: Pre-Emption

    Interrupt return is passed as a data field in the LR, so ISR functions can be normal C/C++ functions, and do not require a veneer. 5-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 97: Table 5-4 Exception Entry Steps

    Exceptions Table 5-4 describes the steps that the Cortex-M3 processor takes before it enters an ISR. Table 5-4 Exception entry steps Action Restartable? Description Push eight Pushes xPSR, PC, r0, r1, r2, r3, r12, and LR on selected stack. registers Read vector table Yes.

  • Page 98: Figure 5-2 Exception Entry Timing

    (3'b001). Prior to that it indicates which ISR is being fetched. Figure 5-2 shows that there is a 12-cycle latency from asserting the interrupt to the first instruction of the ISR executing. 5-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 99: Tail-Chaining

    ETMINTNUM remains asserted throughout the duration of the ISR. Figure 5-3 shows that there is a 6-cycle latency from returning from the last ISR to executing the new ISR. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-13...

  • Page 100: Late-Arriving

    INTISR[8] can preempt before the first instruction of the ISR for INTISR[2] enters Execute stage. A higher priority interrupt after that point is managed as a pre-emption. 5-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 101 CURRPRI[7:0] indicates the priority of the active interrupt. CURRPRI remains asserted throughout the duration of the ISR. • ETMINTNUM[8:0] indicates the number of the active interrupt. ETMINTNUM remains asserted throughout the duration of the ISR. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-15...

  • Page 102: Exit

    Because of dynamic priority changes, the NVIC uses interrupt numbers instead of interrupt priorities to determine which ISR is current. Figure 5-5 on page 5-17 shows an example of exception exit timing. 5-16 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 103: Figure 5-5 Exception Exit Timing

    Exception returns occur when one of the following instructions loads a value of into the PC: 0xFFFFFFFX • POP/LDM which includes loading the PC • LDR with PC as a destination • BX with any register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-17...

  • Page 104: Table 5-6 Exception Return Behavior

    This address range is defined to have Execute Never (XN) permissions, and will result in a MemManage fault. 5-18 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 105: Resets

    An example of a full vector table: unsigned int stack_base[STACK_SIZE]; void ResetISR(void); void NmiISR(void); … ISR_VECTOR_TABLE vector_table_at_0 stack_base + sizeof(stack_base), ResetISR, NmiSR, FaultISR, // Populate if using MemManage (MPU) ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-19...

  • Page 106: Table 5-8 Reset Boot-Up Behavior

    Optionally change vector table from Code area, @0, to a location in SRAM. This is only done to optimize performance or allow dynamic changes. [Setup Configurable Faults] Enable Configurable faults and set their priorities. Setup interrupts Setup priority levels and masks. 5-20 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 107 Example 5-2 Reset routine with selected Sleep model using WFI void reset() extern volatile unsigned exc_req; // do setup work (initialize variables, initialize runtime if wanted, ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-21...
  • Page 108 For RTOS models using threads and privilege, the Thread Mode is used for the user code. 5-22 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 109: Exception Control Transfer

    Exception postamble If the new exception has higher priority than the stacked exception to which the processor is returning, the processor tail-chains the new exception. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-23...

  • Page 110: Setting Up Multiple Stacks

    MSR PSP, r0 ; set Process stack value ORR lr, lr, #4 ; change EXC_RETURN for return on PSP BX lr ; return from Handler to Thread 5-24 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 111 Thread from MSP to PSP can be made, or the non-stacked registers can be guaranteed not to have been modified by a stacked Handler, is when there is only one ISR/Handler active. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-25...

  • Page 112: Abort Model

    • an exception handler causes a fault with the same or higher priority • the local fault is not enabled. 5-26 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 113: Table 5-10 Faults

    Branch shadow can fault and be ignored. Precise Data bus error PRECISEERR BusFault Bus error returned because of data BUSERR access, and was precise, points to instruction. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-27...
  • Page 114 This can be enabled to occur when CHKERR SDIV or UDIV is executed with a divisor of 0, and the DIV_0_TRP bit is set. SVCall System request (Service Call). 5-28 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 115: Table 5-11 Debug Faults

    BFAR and MMFAR are the same physical register. Because of this the BFARVALID and MMFARVALID bits are mutually exclusive. Table 5-12 on page 5-30 shows the fault status registers and two fault address registers ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-29...

  • Page 116: Table 5-12 Fault Status And Fault Address Registers

    Escalation and Special MMSR Mem Manage MMAR MPU faults BFSR Bus Fault BFAR Bus faults UFSR Usage Fault Usage fault DFSR Debug Monitor or Halt Debug traps 5-30 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 117: Activation Levels

    Debug event when halting not Debug monitor Synchronous Privileged Main enabled SVC instruction External interrupt a. Interrupt service routine. b. Nonmaskable interrupt. c. Coprocessor. d. Software interrupt. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-31...

  • Page 118: Table 5-15 Exception Subtype Transitions

    Boosts priority of local handler to same as hard fault so it can Configurable fault return and chain to Configurable Fault handler handler a. While halting not enabled. 5-32 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 119: Flowcharts

    Pending interrupt higher priority than PC at return location? active interrupt? Preempt Pending interrupt higher priority than stacked interrupt? Return from interrupt Figure 5-6 Interrupt handling flowchart ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-33...

  • Page 120: Figure 5-7 Pre-Emption Flowchart

    Return Figure 5-8 on page 5-35 shows how the processor restores the stacked ISR or tail-chains to a late-arriving interrupt with higher priority than the stacked ISR. 5-34 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 121: Figure 5-8 Return From Interrupt Flowchart

    Exceptions Figure 5-8 Return from interrupt flowchart ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 5-35...
  • Page 122 Exceptions 5-36 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 123 This chapter describes the processor clocking and resets. It contains the following sections: • Cortex-M3 clocking on page 6-2 • Cortex-M3 resets on page 6-4 • Cortex-M3 reset modes on page 6-5. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 124: Chapter 6 Clocking And Resets

    FCLK and HCLK are synchronous to each other. FCLK is a free running version of HCLK. For more information, see Chapter 7 Power Management. FCLK and HCLK must be balanced with respect to each other, with equal latencies into Cortex-M3. The processor is integrated with components for debug and trace. Your macrocell may contain some, or all, of the clocks shown in Table 6-2.
  • Page 125 Clocking and Resets Note Cortex-M3 also contains a STCLK input. This port is not a clock. It is a reference input for the SysTick counter, and it must be less than half the frequency of FCLK. STCLK is synchronized internally by the processor to FCLK.

  • Page 126: Cortex-M3 Resets

    Resets the entire processor system with the exception of debug logic in the NVIC, FPB, DWT, ITM, and AHB-AP nTRST JTAG-DP reset Note nTRST resets JTAG-DP. If your implementation doesn't contain JTAG-DP, this reset must be tied off. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 127: Cortex-M3 Reset Modes

    Reset of JTAG-DP logic. Note PORESETn resets a superset of the SYSRESETn logic. 6.3.1 Power-on reset Figure 6-1 on page 6-6 shows the reset signals for the macrocell. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 128: Figure 6-1 Reset Signals

    It is recommended that you assert the reset signals for at least three HCLK cycles to ensure correct reset behavior. Figure 6-3 on page 6-7 shows the internal reset synchronization. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 129: Figure 6-3 Internal Reset Synchronization

    Clocking and Resets Note LOCKUP from the Cortex-M3 system should be considered for inclusion in any external watchdog circuitry when an external debugger is not attached. Figure 6-3 Internal reset synchronization 6.3.2 System reset A system or warm reset initializes the majority of the macrocell, excluding the NVIC debug logic, Flash Patch and Breakpoint (FPB), Data Watchpoint and Trigger (DWT), and Instruction Trace Macrocell (ITM).
  • Page 130 Normal operation During normal operation, neither processor reset nor power-on reset is asserted. If the JTAG-DP port is not being used, the value of nTRST does not matter. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 131 Power Management This chapter describes the processor power management functions. It contains the following sections: • About power management on page 7-2 • System power management on page 7-3 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 132: Chapter 7 Power Management

    The ARMv7-M architecture supports system sleep modes that enable the Cortex-M3 and system clocks to be stopped for greater power reductions. These are described in System power management on page 7-3.

  • Page 133: System Power Management

    Power Management System power management Writing to the System Control Register (see System Control Register on page 8-23) controls the Cortex-M3 system power states. Table 7-1 shows the supported sleep modes. Table 7-1 Supported sleep modes Sleep mechanism Description Sleep-now The Wait For Interrupt (WFI) or the Wait For Event (WFE) instructions request the sleep-now model.

  • Page 134: Figure 7-1 Sleeping Power Control Example

    SLEEPDEEP in the low-power state. When exiting low-power state, the LOCK signal indicates that the PLL is stable, and it is safe to enable the Cortex-M3 clock, ensuring that the processor is not re-started until the clocks are stable.

  • Page 135: Figure 7-2 Sleepdeep Power Control Example

    Figure 7-2 SLEEPDEEP power control example To detect interrupts, the processor must receive the free-running FCLK in the low-power state. FCLK frequency can be reduced during SLEEPDEEP assertion. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 136 Power Management Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 137 This chapter describes the Nested Vectored Interrupt Controller (NVIC). It contains the following sections: • About the NVIC on page 8-2 • NVIC programmer’s model on page 8-3 • Level versus pulse interrupts on page 8-40. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 138: Chapter 8 Nested Vectored Interrupt Controller

    All NVIC registers and system debug registers are little endian regardless of the endianness state of the processor. Processor exception handling is described in Chapter 5 Exceptions. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 139: Nvic Programmer's Model

    Read/write page 8-12 0x00000000 Irq 224 to 239 Set Enable Register Read/write 0xE000E11C page 8-12 0x00000000 Irq 0 to 31 Clear Enable Register Read/write 0xE000E180 page 8-13 0x00000000 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 140 Irq 224 to 239 Active Bit Register Read-only page 8-15 0xE000E400 Irq 0 to 31 Priority Register Read/write page 8-15 0x00000000 Irq 236 to 239 Priority Register Read/write 0xE000E4F0 0x00000000 page 8-15 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 141 MMFR1: Memory Model Feature register1 Read-only 0xE000ED54 0x00000000 MMFR2: Memory Model Feature register2 Read-only 0xE000ED58 0x00000000 MMFR3: Memory Model Feature register3 Read-only 0xE000ED5C 0x00000000 ISAR0: ISA Feature register0 Read-only 0xE000ED60 0x01141110 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 142 0xE000EFF8 Component identification register Bits 23:16 Read-only 0x05 (PCELLID2) 0xE000EFFC Component identification register Bits 31:24 Read-only 0xB1 (PCELLID3) a. Reset value depends on the number of interrupts defined. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 143: Figure 8-1 Interrupt Controller Type Register Bit Assignments

    Depends on the number of interrupts defined in this implementation of Cortex-M3. Figure 8-1 shows the fields of the Interrupt Controller Type Register. Reserved INTLINESNUM Figure 8-1 Interrupt Controller Type Register bit assignments ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 144: Table 8-2 Interrupt Controller Type Register Bit Assignments

    = 161...192 b00110 = 193...224 b00111 = 225...256* *Cortex-M3 processor only supports between 1 and 240 external interrupts. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The register address, access type, and Reset state are:...

  • Page 145: Table 8-3 Systick Control And Status Register Bit Assignments

    RELOAD. The register address, access type, and Reset state are: Address 0xE000E014 Access Read/write Reset state Unpredictable Figure 8-3 shows the fields of the SysTick Reload Value Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 146: Table 8-4 Systick Reload Value Register Bit Assignments

    Address 0xE000E018 Access Read/write clear Reset state Unpredictable Figure 8-4 shows the fields of the SysTick Current Value Register. Figure 8-4 SysTick Current Value Register bit assignments 8-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 147: Table 8-5 Systick Current Value Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000E01C Access Read Reset state STCALIB Figure 8-5 describes the fields of the SysTick Calibration Value Register. Figure 8-5 SysTick Calibration Value Register bit assignments ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-11...

  • Page 148: Table 8-6 Systick Calibration Value Register Bit Assignments

    Clearing an Interrupt Set-Enable Register bit does not affect currently active interrupts. It only prevents new activations. The register address, access type, and Reset state are: Address 0xE000E100-0xE000E11C Access Read/write Reset state 0x00000000 8-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 149: Table 8-7 Bit Functions Of The Interrupt Set-Enable Register

    Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current state. Interrupt Set-Pending Register Use the Interrupt Set-Pending Register to: • force interrupts into the pending state • determine which interrupts are currently pending. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-13...

  • Page 150: Table 8-9 Bit Functions Of The Interrupt Set-Pending Register

    Clear-Pending Register bit puts the corresponding pending interrupt in the inactive state. Note Writing to the Interrupt Clear-Pending Register has no effect on an interrupt that is active unless it is pending as well. 8-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 151: Table 8-10 Bit Functions Of The Interrupt Clear-Pending Registers

    Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-15...

  • Page 152: Figure 8-6 Interrupt Priority Registers 0-31 Bit Assignments

    Figure 8-6 shows the fields of Interrupt Priority Registers 0-7. Figure 8-6 Interrupt Priority Registers 0-31 bit assignments The lower PRI_n bits can specify subpriorities for priority grouping. See Exception priority on page 5-5. 8-16 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 153: Table 8-12 Interrupt Priority Registers 0-31 Bit Assignments

    Table 8-13 describes the fields of the CPUID Base Register. Table 8-13 CPUID Base Register bit assignments Field Name Definition [31:24] IMPLEMENTER Implementer code. ARM is 0x41 [23:20] VARIANT Implementation defined variant number. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-17...
  • Page 154 The register address, access type, and Reset state are: Address 0xE000ED04 Access Read/write or read-only Reset state 0x00000000 Figure 8-8 on page 8-19 shows the fields of the Interrupt Control State Register. 8-18 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 155: Table 8-14 Interrupt Control State Register Bit Assignments

    1 = set pending SysTick 0 = do not set pending SysTick. [25] PENDSTCLR Write-only Clear pending SysTick bit: 1 = clear pending SysTick 0 = do not clear pending SysTick. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-19...
  • Page 156 The register address, access type, and Reset state are: Address 0xE000ED08 Access Read/write Reset state 0x00000000 Figure 8-9 on page 8-21 shows the fields of the Vector Table Offset Register. 8-20 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 157: Table 8-15 Vector Table Offset Register Bit Assignments

    • alter the priority grouping position (binary point). The register address, access type, and Reset state are: Address 0xE000ED0C Access Read/write Reset state 0x00000000 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-21...

  • Page 158: Table 8-16 Application Interrupt And Reset Control Register Bit Assignments

    2.6 indicates two bits of pre-emption priority, six bits of subpriority 1.7 indicates one bit of pre-emption priority, seven bits of subpriority 0.8 indicates no pre-emption priority, eight bits of subpriority 8-22 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 159 System Control Register Use the System Control Register for power-management functions: • signal to the system when the Cortex-M3 processor can enter a low power state • control how the processor enters and exits low power states. The register address, access type, and Reset state are:...

  • Page 160: Table 8-17 System Control Register Bit Assignments

    SLEEPDEEP Sleep deep bit: 1 = indicates to the system that Cortex-M3 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped. 0 = not OK to turn off system clock.

  • Page 161: Table 8-18 Configuration Control Register Bit Assignments

    Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault Status Register on page 8-33. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-25...
  • Page 162 The register addresses, access types, and Reset states are: Address 0xE000ED18 0xE000ED1C 0xE000ED20 Access Read/write Reset state 0x00000000 Figure 8-13 on page 8-27 shows the fields of the System Handler Priority Registers. 8-26 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 163: Table 8-19 System Handler Priority Registers Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED24 Access Read/write Reset state 0x00000000 Figure 8-14 on page 8-28 shows the fields of the System Handler and State Control Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-27...

  • Page 164: Table 8-20 System Handler Control And State Register Bit Assignment

    Reads as 1 if MemManage is pended Started to invoke, but was replaced by a higher priority interrupt. [12] Reserved [11] SYSTICKACT Reads as 1 if SysTick is active. [10] PENDSVACT Reads as 1 if PendSV is active. 8-28 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 165 SVCall or BusFault handler is started, the bits are not cleared. This enables the push-error or vector-read-error handler to choose to clear them or retry ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-29...

  • Page 166: Figure 8-15 Local Fault Status Registers Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED28 Access Read/write clear Reset state 0x00000000 Figure 8-16 on page 8-31 shows the fields of the Memory Manage Fault Status Register. 8-30 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 167: Table 8-21 Memory Manage Fault Status Register Bit Assignments

    MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written. Bus Fault Status Register The flags in the Bus Fault Status Register indicate the cause of bus access faults. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-31...

  • Page 168: Table 8-22 Bus Fault Status Register Bit Assignments

    SP is not adjusted from failing return and new save is not performed. The BFAR is not written. 8-32 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 169 The register address, access type, and Reset state are: Address 0xE000ED2B Access Read/write clear Reset state 0x00000000 Figure 8-18 on page 8-34 shows the fields of the Usage Fault Status Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-33...

  • Page 170: Table 8-23 Usage Fault Status Register Bit Assignments

    This is an instruction that could not be decoded. The return PC points to the undefined instruction. Note The fault bits are additive if more than one fault occurs before this register is cleared. 8-34 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 171: Table 8-24 Hard Fault Status Register Bit Assignments

    This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the preempted instruction. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-35...

  • Page 172: Figure 8-20 Debug Fault Status Register Bit Assignments

    Address 0xEEE0ED30 Access Read/write clear Reset state 0x00000000 Figure 8-20 shows the fields of the Debug Fault Status Register. Figure 8-20 Debug Fault Status Register bit assignments 8-36 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 173: Table 8-25 Debug Fault Status Register Bit Assignments

    Use the Memory Manage Fault Address Register to read the address of the location that caused a Memory Manage Fault. The register address, access type, and Reset state are: Address 0xE000ED34 Access Read/write Reset state Unpredictable ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-37...

  • Page 174: Table 8-26 Bit Functions Of The Memory Manage Fault Address Register

    The register address, access type, and Reset state are: Address 0xE000EF00 Access Write-only Reset state 0x00000000 Figure 8-21 on page 8-39 shows the fields of the Software Trigger Interrupt Register. 8-38 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 175: Table 8-28 Software Trigger Interrupt Register Bit Assignments

    Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 8-39...

  • Page 176: Level Versus Pulse Interrupts

    The processor supports both level and pulse interrupts. A level interrupt is held asserted until it is cleared by the ISR accessing the device. A pulse interrupt is a variant of an edge model. The edge must be sampled on the rising edge of the Cortex-M3 clock, HCLK, instead of being asynchronous.
  • Page 177 Interrupts and updating the MPU on page 9-19 • MPU access permissions on page 9-13 • MPU aborts on page 9-15 • Updating an MPU region on page 9-16. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 178: Chapter 9 Memory Protection Unit

    MemManage fault handler. For more information, see Memory Manage Fault Address Register on page 8-37. You can use the MPU to: • enforce privilege rules • separate processes • enforce access rules. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 179: Mpu Programmer's Model

    Use the MPU Type Register to see how many regions the MPU supports. Read bits [15:8] to determine if an MPU is present. The register address, access type, and Reset state are: Address 0xE000ED90 Access Read-only ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 180: Table 9-2 Mpu Type Register Bit Assignments

    When the MPU is enabled, only the system partition and vector table loads are always accessible. Other areas are accessible based on regions and whether PRIVDEFENA is enabled. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 181: Figure 9-2 Mpu Control Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED94 Access Read/write Reset state 0x00000000 Figure 9-2 shows the fields of the MPU Control Register. Figure 9-2 MPU Control Register bit assignments ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 182: Table 9-3 Mpu Control Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED98 Access Read/write Reset state Unpredictable Figure 9-3 on page 9-7 shows the fields of the MPU Region Number Register. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 183: Table 9-4 Mpu Region Number Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED9C Access Read/write Reset state Unpredictable Figure 9-4 on page 9-8 shows the fields of the MPU Region Base Address Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 184: Table 9-5 Mpu Region Base Address Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000EDA0 Access Read/write Reset state Unpredictable Figure 9-5 on page 9-9 shows the fields of the MPU Region Attribute and Size Register. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 185: Table 9-6 Mpu Region Attribute And Size Register Bit Assignments

    [23:22] Reserved. [21:19] Type extension field. [18] Shareable bit: 1 = shareable 0 = not shareable. [17] Cacheable bit: 1 = cacheable 0 = not cacheable. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 186: Table 9-7 Mpu Protection Region Size Field

    Table 9-7 MPU protection region size field Region Size b00000 Reserved b00001 Reserved b00010 Reserved b00011 Reserved b00100 b00101 b00110 128B b00111 256B b01000 512B b01001 b01010 b01011 b01100 b01101 16KB 9-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 187 The aliases access the registers in exactly the same way, and they exist to enable the use of sequential writes (STM) to update between one and four regions. This is used when disable/change/enable is not required. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 9-11...
  • Page 188 512KB. The bottom 64KB of the 512KB region is disabled so that the attributes from the 64KB apply. This is achieved by setting SRD for the 512KB region to b11111110. 9-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 189: Mpu Access Permissions

    Cached memory BB = outer policy. AA = inner Normal policy Note In Table 9-8, ‘S’ is the S bit[2] from the MPU Region Attributes and Size Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 9-13...

  • Page 190: Table 9-9 Cache Policy For Memory Attribute Encoding

    Privileged/user read only Read only Read only Privileged/user read only Table 9-11 describes the XN encoding. Table 9-11 XN encoding Description All instruction fetches enabled No instruction fetches enabled 9-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 191: Mpu Aborts

    Memory Protection Unit MPU aborts For information about MPU aborts, see Memory Manage Fault Address Register on page 8-37. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 9-15...

  • Page 192: Updating An Mpu Region

    ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address R0,#NVIC_BASE 9-16 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 193 R3,[R0,#8] ; size, attributes This can be optimized using an STM: ; R1 = region number ; R2 = address ; R3 = size, attributes in one ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 9-17...
  • Page 194 ; R2 = size and attributes in one R0,#NVIC_BASE R0,#MPU_REG_CTRL R0,{R1-R2} ; address, region number, size For information about interrupts and updating the MPU, see Interrupts and updating the MPU on page 9-19. 9-18 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 195: Interrupts And Updating The Mpu

    If those are the only two places, and the context switcher is only updating user regions, then disable is not required because the context switcher is already a critical region and the boot code runs with interrupts disabled. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 9-19...
  • Page 196 Memory Protection Unit 9-20 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 197 About core debug on page 10-2 • Core debug registers on page 10-3 • Core debug access example on page 10-12 • Using application registers in core debug on page 10-13. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 10-1...

  • Page 198: Chapter 10 Core Debug

    S_HALT bit of the Debug Halting Control and Status Register. 10.1.2 Exiting core debug The core can exit Halting debug by clearing the C_DEBUGEN bit in the Debug Halting and Status Register. 10-2 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 199: Core Debug Registers

    The DHCSR is only reset from a system reset, including power on. Bit 16 of DHCSR is UNPREDICTABLE on reset. Figure 10-1 on page 10-4 shows the arrangement of bits in the register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 10-3...

  • Page 200: Table 10-2 Debug Halting Control And Status Register

    This is used to determine if the core is stalled on a load/store or fetch. [23:20] Reserved, RAZ. [19] S_LOCKUP Reads as one if the core is running (not halted) and a lockup condition is present. 10-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 201 The core must write a 1 to it when writing C_HALT to halt itself. If not enabled for Halting mode, C_DEBUGEN = 1, all other fields are disabled. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 10-5...

  • Page 202: Figure 10-2 Debug Core Selector Register Format

    • is a 17-bit write-only register • address is 0xE000EDF4 Figure 10-2 shows the arrangement of bits in the register. Figure 10-2 Debug Core Selector Register format 10-6 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 203: Table 10-3 Debug Core Selector Register

    ICI can be written, though invalid values or when not used on an LDM/STM causes a fault, as would on return from exception. Changing ICI from a value to 0 causes the underlying LDM/STM to start, not continue. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 10-7...
  • Page 204 Debug monitor control. The DEMCR: • is a 32-bit read/write register • address 0xE000EDFC Figure 10-2 on page 10-6 shows the arrangement of bits in the register. 10-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 205: Table 10-4 Debug Exception And Monitor Control Register

    This is the equivalent to C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 10-9...
  • Page 206 CAR register. Debug trap on Memory Management faults (see section 8.3). VC_MMERR [3:1] Reserved, SBZP Reset Vector Catch. Halt running system if Core reset occurs. VC_CORERESET 10-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 207 If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is, an implementation which supports the late arrival optimization must suppress it in this case. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 10-11...

  • Page 208: Core Debug Access Example

    Write the value that you want to be written to the Debug Core Register Data Register. Write the register number that you want to write to into the Debug Core Register Selector Register. 10-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 209: Table 10-5 Application Registers For Use In Core Debug

    Interrupt Control State ISRPREEMPT ISRPENDING VECTPENDING. Vector Table Offset To find vector table Application Interrupt/Reset Control VECTCLRACTIVE ENDIANESS Configuration Control DIV_0_TRP UNALIGN_TRP. System Handler Control and State ACTIVE PENDED ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 10-13...
  • Page 210 Core Debug 10-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 211: About System Debug

    Flash Patch and Breakpoint on page 11-6 • Data Watchpoint and Trace on page 11-12 • Instrumentation Trace Macrocell on page 11-26 • AHB Access Port on page 11-35. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-1...
  • Page 212 All the debug components exist on the internal Private Peripheral Bus (PPB) and can be accessed using privileged code. Note • For a description of the Core debug, see Chapter 10 Core Debug. 11-2 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 213: System Debug Access

    — Trace Port Interface Unit (TPIU). This component acts as a bridge between the Cortex-M3 trace data (from the ITM, and ETM if present) and an off-chip Trace Port Analyzer. See Chapter 13 Trace Port Interface Unit for more information.

  • Page 214: Figure 11-1 System Debug Access Block Diagram

    System Debug Figure 11-1 System debug access block diagram 11-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 215: System Debug Programmer's Model

    For a description of the JTAG-DP and SW-DP registers see Chapter 12 Debug Port. • For a description of the TPIU, see Chapter 13 Trace Port Interface Unit. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-5...
  • Page 216 Note Remapping to the bit-band alias directly accesses the alias address, and does not remap to the bit-band region. 11-6 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 217: Table 11-1 Flash Patch Register Summary

    Value 0x0B 0xE0002FEC PERIPID3 Read-only Value 0x00 0xE0002FF0 PCELLID0 Read-only Value 0x0D 0xE0002FF4 PCELLID1 Read-only Value 0xE0 0xE0002FF8 PCELLID2 Read-only Value 0x05 PCELLID3 Read-only 0xE0002FFC Value 0xB1 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-7...

  • Page 218: Table 11-2 Flash Patch Control Register Bit Assignments

    Key field. To write to the Flash Patch Control Register, you must write a 1 to this write-only bit. ENABLE Flash patch unit enable bit: 1 = flash patch unit enabled 0 = flash patch unit disabled. Reset clears the ENABLE bit. 11-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 219: Table 11-3 Comp Mapping

    The register address, access type, and Reset state are: Address 0xE0002004 Access Read/write Reset state This register is not reset Figure 11-3 shows the fields of the Flash Patch Remap Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-9...

  • Page 220: Table 11-4 Flash Patch Remap Register Bit Assignments

    Figure 11-4 shows the fields of the Flash Patch Comparator Registers. Figure 11-4 Flash Patch Comparator Registers bit assignments Table 11-5 describes the fields of the Flash Patch Comparator Registers. 11-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 221: Table 11-5 Flash Patch Comparator Registers Bit Assignments

    Register n compare and remap enabled 0 = Flash Patch Comparator Register n compare and remap disabled The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-11...

  • Page 222: Table 11-6 Dwt Register Summary

    See DWT CPI Count Register on page 11-18 0xE0001008 DWT_EXCCNT Read/write See DWT Exception Overhead Count Register on 0xE000100C page 11-19 DWT_SLEEPCNT Read/write See DWT Sleep Count Register on page 11-20 0xE0001010 11-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 223 Read-only Value 0x02 0xE0001FE4 0xB0 PERIPHID1 Read-only Value 0xB0 0xE0001FE8 0x0B0 PERIPHID2 Read-only Value 0x0B 0xE0001FEC 0x00 PERIPHID3 Read-only Value 0x00 PCELLID0 Read-only 0xE0001FF0 0x0D Value 0x0D ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-13...

  • Page 224: Figure 11-5 Dwt Control Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE0001000 Access Read/write Reset state 0x40000000 Figure 11-5 shows the fields of the DWT Control Register. Figure 11-5 DWT Control Register bit assignments 11-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 225: Table 11-7 Dwt Control Register Bit Assignments

    Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead). 1 = Interrupt overhead event enabled 0 = Interrupt overhead event disabled Reset clears the EXCEVTENA bit. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-15...
  • Page 226 CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT (bits [8:5]) post-scalar counter. That counter will count-down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT. 11-16 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 227 This count can be used to measure elapsed execution time. The register address, access type, and Reset state are: Address 0xE0001004 Access Read-only Reset state 0x00000000 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-17...

  • Page 228: Table 11-8 Dwt Current Pc Sampler Cycle Count Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE0001008 Access Read-write Reset state Figure 11-6 shows the fields of the DWT CPI Count Register. Figure 11-6 DWT CPI Count Register bit assignments 11-18 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 229: Table 11-9 Dwt Cpi Count Register Bit Assignments

    An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Clears to 0 on enabling. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-19...

  • Page 230: Table 11-11 Dwt Sleep Count Register Bit Assignments

    Use the DWT LSU Count Register to count the total number of cycles during which the processor is processing an LSU operation beyond the first cycle. The register address, access type, and Reset state are: Address 0xE0001014 Access Read/write Reset state 11-20 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 231: Table 11-12 Dwt Lsu Count Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE0001018 Access Read/write Reset state Figure 11-10 describes the fields of the DWT Fold Count Register. Figure 11-10 DWT Fold Count Register bit assignments ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-21...

  • Page 232: Table 11-13 Dwt Fold Count Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE0001024 0xE0001034 0xE0001044 0xE0001054 Access Read/write Reset state Figure 11-11 on page 11-23 shows the fields of DWT Mask Registers 0-3. 11-22 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 233: Table 11-15 Dwt Mask Registers 0-3 Bit Assignments

    The register address, access type, and Reset state are: Address 0xE0001028, 0xE0001038 0xE0001048 0xE0001058 Access Read/write Address 0x00000000 Figure 11-12 on page 11-24 shows the fields of DWT Function Registers 0-3. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-23...

  • Page 234: Table 11-17 Settings For Dwt Function Registers

    EMITRANGE=0, sample PC and data value through ITM on read or write. EMITRANGE=1, emit address offset and data value through ITM on read or write. b0100 Watchpoint on PC match. 11-24 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 235 • PC match is not recommended for watchpoints because it stops after the instruction - it is mainly used for guards and for ETM triggering. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-25...

  • Page 236: Table 11-18 Itm Register Summary

    Time stamping. Timestamps are emitted relative to packets. ITM contains a 21-bit counter to generate the timestamp. The counter is clocked using either the Cortex-M3 clock, or the bitclock rate of the SWV output. 11.6.1 Summary and description of the ITM registers...
  • Page 237 Stimulus Registers and Trace Enable Registers can be written, and only when the corresponding Trace Privilege Register bit is set. Invalid User mode writes to the ITM registers is discarded. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-27...

  • Page 238: Table 11-19 Bit Functions Of The Itm Trace Enable Register

    1 = not Full) in bit 0. The polled FIFO interface does not provide an atomic read-modify-write, so the Cortex-M3 exclusive monitor must be used if a polled printf is used concurrently with ITM usage by interrupts or other threads. The following polled code guarantees stimulus is not lost by polled access to the ITM: ;...

  • Page 239: Table 11-20 Bit Functions Of The Itm Trace Privilege Register

    Bit mask to enable tracing on ITM stimulus ports: bit[0] = stimulus ports [7:0] bit[1] = stimulus ports [15:8] bit[2] = stimulus ports [23:16] bit[3] = stimulus ports [31:24]. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-29...

  • Page 240: Table 11-21 Bit Functions Of The Itm Control Register

    ATB ID for CoreSight system [15:10] 0b000000 [9:8] TSPrescale Timestamp prescaler 0b00 = no prescaling 0b01 = divide by 4 0b10 = divide by 16 0b11 = divide by 64 11-30 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 241: Figure 11-15 Itm Integration Write Register Bit Assignments

    Use this register to determine the behavior of the ATVALIDM bit. Figure 11-15 shows the ITM Integration Write Register bit assignments. Figure 11-15 ITM Integration Write Register bit assignments ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-31...

  • Page 242: Table 11-22 Bit Functions Of The Itm Integration Write Register

    Table 11-23 Bit functions of the ITM Integration Read Register Field Name Definition [31:1] Reserved ATREADYM Value on ATREADYM ITM Integration Mode Control Register Use this register to enable write accesses to the Control Register. 11-32 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 243: Table 11-24 Bit Functions Of The Itm Integration Mode Control Register

    ITM Lock Status Register Use this register to enable write accesses to the Control Register. Figure 11-18 on page 11-34 shows the ITM Lock Status Register bit assignments. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-33...

  • Page 244: Table 11-26 Bit Functions Of The Itm Lock Status Register

    You cannot implement 8-bit lock accesses Access Write access to component is blocked. All writes are ignored, reads are permitted. Present Indicates that a lock mechanism exists for this component 11-34 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 245: Table 11-27 Ahb-Ap Register Summary

    AHB Access Port The Advanced High-performance Bus Access Port (AHB-AP) is a debug access port into Cortex-M3, and provides access to all memory and registers in the system, including processor registers (through the NVIC). System access is independent of the processor status.

  • Page 246: Figure 11-19 Ahb-Ap Control And Status Word Register

    Use this register to configure and control transfers through the AHB interface. Figure 11-19 shows the fields of the AHB-AP Control and Status Word Register. Figure 11-19 AHB-AP Control and Status Word Register 11-36 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 247: Table 11-28 Bit Functions Of The Ahb-Ap Control And Status Word Register

    Indicates the status of the DBGEN port. If DbgStatus is LOW, no AHB transfers carried out. 1 = AHB transfers permitted. 0 = AHB transfers not permitted. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-37...

  • Page 248: Table 11-29 Ahb-Ap Transfer Address Register Bit Functions

    Table 11-29 describes the fields of the AHB-AP Transfer Address Register. Table 11-29 AHB-AP Transfer Address Register bit functions Field Name Definition [31:0] ADDRESS Current transfer address. Reset value = 0x00000000 11-38 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 249: Table 11-30 Bit Functions Of The Ahb-Ap Data Read/Write Register

    Banked transfers are only supported for word transfers. Non-word banked transfer size is currently ignored, assumed word access. Reset value - 0x00000000 AHB-AP Debug ROM Address Register This register specifies the base address of the debug interface. It is read-only. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 11-39...

  • Page 250: Table 11-32 Bit Functions Of The Ahb-Ap Debug Rom Address Register

    This field is zero for the first implementation of an AP design, and is updated for each major revision of the design. [27:24] JEP-106 continuation code For an ARM-designed AP, this field has value 0b0100, [23:17] JEP-106 identity code For an ARM-designed AP, this field has value 0b0111011,...
  • Page 251 • JTAG-DP on page 12-3 • SW-DP on page 12-20 • Common Debug Port (DP) features on page 12-41 • Debug Port Programmer’s Model on page 12-47. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-1...

  • Page 252: About The Debug Port

    AHB-AP port. For more information, see AHB Access Port on page 11-35. These alternative DP implementations provide different mechanisms for debug access to Cortex-M3. Your implementation might contain either, or both, of these components. Note • Only one DP can be used at once, and switching between the two debug ports should only be performed when neither DP is in use.

  • Page 253: Table 12-1 Jtag-Dp Signal Connections

    JTAG-DP. It is based closely on the JTAG TAP State Machine, see IEEE Std 1149.1-1990. This chapter describes both the JTAG-DP and its scan chain interface. Figure 12-1 on page 12-4 shows an ARM Debug Interface with a JTAG-DP, including the operation of the scan chain interface.

  • Page 254: Figure 12-1 Jtag-Dp Physical Connection

    The recommended physical connection to the JTAG-DP is shown in Figure 12-1. Figure 12-1 JTAG-DP physical connection The DAP State Machine (JTAG) Figure 12-2 on page 12-5 shows the JTAG state machine. 12-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 255: Figure 12-2 The Dap State Machine (Jtag)

    Debug Port Figure 12-2 The DAP State Machine (JTAG) When using an ARM Debug Interface, for the debug process to work correctly, systems must not remove power from the JTAG-DP during a debug session. If power is removed, the DAP controller state is lost. However, the DAP is designed to enable the rest of the DAP and the core to be powered down and debugged, while maintaining power to the JTAG-DP.
  • Page 256 Note This is a change from the behavior of previous versions of the ARM Debug Interface based on the IEEE JTAG standard. From ARM Debug Interface v5, debuggers do not have to gate the DAP clock to obtain a true rest state.

  • Page 257: Figure 12-3 Jtag Instruction Register Bit Order

    Order Figure 12-3 shows the bit order of the Instruction Register. Figure 12-3 JTAG Instruction Register bit order This register is mandatory in the IEEE 1149.1 standard. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-7...

  • Page 258: Table 12-2 Standard Ir Instructions

    IEEE 1149.1 compliance. The required instructions are listed in Table 12-3 on page 12-9. Note • ARM Limited recommends that separate JTAG TAPs are used for boundary scan and debug. • If the IR register is set to an IR instruction value that is not implemented, or reserved, then the Bypass Register is selected.

  • Page 259: Table 12-3 Recommended Implementation-Defined Ir Instructions For Ieee 1149.1-Compliance

    CLAMPZ can be implemented to ensure that, during production test, each output can be disabled when its value is 0 or 1. This encoding should be used if this function is required. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-9...

  • Page 260: Figure 12-4 Jtag Bypass Register Operation

    Device ID Codes, so that a debugger can make this distinction. This is the JTAG-DP implementation of the Identification Code Register, see The Identification Code Register, IDCODE on page 12-52. 12-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 261: Figure 12-5 Jtag Device Id Code Register Bit Order

    AHB-AP registers on page 11-35 for details of accessing AHB-AP registers, and JTAG-DP Registers on page 12-47 for details of accessing JTAG-AP registers. Length 35 bits. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-11...

  • Page 262: Table 12-4 Dpacc And Apacc Ack Responses

    OK/FAULT or WAIT. The two cases are described in: — Update-DR operation following an OK/FAULT response on page 12-13 — Update-DR operation following a WAIT response on page 12-15. 12-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 263: Figure 12-6 Bit Order Of Jtag Dp And Ap Access Registers

    AP register. In either case: • If RnW is shifted in as 0, the request is to write the value in DATAIN[31:0] to the addressed register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-13...
  • Page 264 12-44. Pushed operations are enabled using the TRNMODE field of the DP CTRL/STAT register, see The Control/Status Register, CTRL/STAT on page 12-53 for more information. 12-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 265 12-53 for more information about the Overrun Detect and Sticky Overrun flags. While the previous transaction remains not completed, subsequent scans also receive a WAIT response. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-15...
  • Page 266 WAIT response if Capture-DR is entered before this limit has expired. Although any debugger must be able to recover successfully from any WAIT response, ARM Limited recommends that debuggers should be able to adapt to any Implementation-defined limit.

  • Page 267: Table 12-5 Jtag Target Response Summary

    The Previous scan is the most recent scan for which the ACK response at the Capture-DR state was OK/FAULT. Updates made following a WAIT response are discarded. b. ADDR[3:2] in the DPACC or APACC access. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-17...

  • Page 268: Table 12-6 Summary Of Jtag Host Responses

    When the ABORT instruction is the current instruction in the IR, the serial path between TDI and TDO is connected to a 35-bit scan chain that is used to access the Abort Register. 12-18 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 269: Figure 12-7 Jtag-Dp Abort Scan Chain Bit Order

    The effect of writing any other value into this scan chain is Unpredictable. Order Figure 12-7 shows the bit order of the ABORT scan chain. Figure 12-7 JTAG-DP ABORT scan chain bit order ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-19...

  • Page 270: Sw-Dp

    12.3 SW-DP This section gives an architectural description of the ARM Serial Wire Debug (SW-DP) interface. In particular, it describes the Serial Wire Debug (SWD) protocol, and how this protocol provides access to the DP registers. These registers are described in detail in Debug Port Programmer’s Model on page 12-47.
  • Page 271 HIGH, or reset, by the host until the interface must be activated. Line turn-round To avoid contention, a turnaround period is required when the device driving the wire changes. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-21...
  • Page 272 The terms used in the illustrations are described in Key to illustrations of operations. Key to illustrations of operations The illustrations of the different possible operations use the following terms: Start A single start bit, with value 1. 12-22 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 273 A single bit. The host does not drive the line for this bit, and the line is pulled high by the SWD interface hardware. The target reads this bit as 1. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-23...
  • Page 274 Trn in Key to illustrations of operations on page 12-22 for more information. A successful write operation is shown in Figure 12-8 on page 12-25. 12-24 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 275: Figure 12-8 Serial Wire Debug Successful Write Operation

    By default, there are single-cycle turnaround periods between these two phases, and after the second phase. See the description of Trn in Key to illustrations of operations on page 12-22 for more information. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-25...

  • Page 276: Figure 12-10 Serial Wire Debug Wait Response To A Packet Request

    Figure 12-11 Serial Wire Debug FAULT response to a packet request Note If Overrun Detection is enabled then a data phase is required on a FAULT response. For more information see Sticky overrun behavior on page 12-30. 12-26 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 277: Figure 12-12 Serial Wire Debug Protocol Error After A Packet Request

    It issues an OK response, indicated by an acknowledge phase of b001, if it is ready for the data phase of the transfer, if one is required. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-27...
  • Page 278 Issuing the last AP read packet request returns the last-but-one AP read result. • You must then read the DP RDBUFF Register to obtain the last AP read result. 12-28 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 279 AP or DP access is outstanding • if the new request is an AP read request and the result of the previous AP read is not yet available. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-29...
  • Page 280 • if the transaction is a read the data in the data phase is Unpredictable • if the transaction is a write the data phase is ignored. 12-30 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 281: Figure 12-13 Serial Wire Wait Or Fault Response To A Read Operation When Overrun Detection Is Enabled

    AP. Although this is unlikely, the possibility is a significant consideration, because reads are pipelined and the AP can implement a FIFO. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-31...
  • Page 282 DP operation other than a read of the IDCODE or CTRL/STAT Register, or a write of the ABORT Register. Attempting these operations causes WAIT responses from the DP, until the write buffer is empty. 12-32 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 283: Table 12-7 Target Response Summary For Dp Read Transaction Requests

    Respond with RESEND value from previous AP read. Respond with RDBUF value from previous AP read, and set READOK flag in CTRL/STAT Register. WAIT No data phase, unless overrun detection is enabled ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-33...

  • Page 284: Table 12-8 Target Response Summary For Ap Read Transaction Requests

    DP. See The AP Select Register, SELECT on page 12-57. d. See Sticky overrun behavior on page 12-30 for details of data phase when overrun detection is enabled. 12-34 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 285: Table 12-9 Target Response Summary For Dp Write Transaction Requests

    See Access Port write buffering on page 12-32 for more information. b. See Sticky overrun behavior on page 12-30 for details of data phase when overrun detection is enabled. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-35...

  • Page 286: Table 12-10 Target Response Summary For Ap Write Transaction Requests

    Every access by a debugger to a SW-DP starts with an operation request. Summary of target responses on page 12-33 listed all possible requests from a debugger, and summarized how the SW-DP responds to each request. 12-36 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 287: Table 12-11 Summary Of Host (Debugger) Responses To The Sw-Dp Acknowledge

    DAP internal bus transfers. It shows when the target responds with a WAIT acknowledgement. Figure 12-15 on page 12-38 shows the effect of signalling ACK = WAIT on the length of the packet. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-37...

  • Page 288: Table 12-12 Terms Used In Sw-Dp Timing

    WD[1], can be accepted by the serial engine, while a previous write transfer, WD[0], is completing. Any subsequent transfer must be stalled until the first transfer completes. 12-38 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 289: Figure 12-16 Sw-Dp To Dap Bus Timing For Writes

    It is still necessary to return data to ensure that the protocol timing remains predictable. Figure 12-17 SW-DP to DAP bus timing for reads ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-39...

  • Page 290: Figure 12-18 Sw-Dp Idle Timing

    After the last bit in a packet, the line can be LOW, or idle, for any period longer than a single bit, to enable the Start bit to be detected for back-to-back transactions. 12-40 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 291: Common Debug Port (Dp) Features

    APACC transactions, to check if an error occurred. If a sticky flag is set, the debugger can clear the flag and then, if necessary, initiate more APACC transactions to ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-41...
  • Page 292 If a new transaction is attempted, and results in an overrun error, before an earlier transaction has completed, the first transaction still completes normally. Other sticky flags might be set on completion of the first transaction. 12-42 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 293 CTRL/STAT register and check the sticky flag values. The WDATAERR flag is cleared by writing b1 to the WDERRCLR field of the Abort Register, see The Abort Register, ABORT on page 12-49. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-43...

  • Page 294: Figure 12-19 Pushed Operations Overview

    For more information about this masking see MASKLANE and the bit masking of the pushed compare and pushed verify operations on page 12-56. Figure 12-19 gives an overview of the pushed operations. Figure 12-19 Pushed operations overview 12-44 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 295 Write to the Transfer Address Register (TAR) to indicate the start address of the Debug Register region that is to be verified, see AHB-AP Transfer Address Register on page 11-38. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-45...
  • Page 296 You could also use pushed find without address incrementing to poll a single location, for example to test for a flag being set on completion of an operation. 12-46 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 297: Table 12-13 Jtag-Dp Register Map

    Debug Port 12.5 Debug Port Programmer’s Model Every Cortex-M3 system includes one, or both of: • a JTAG Debug Port (JTAG-DP) • a Serial Wire Debug Port (SW-DP). This section contains: • JTAG-DP Registers. This contains a summary of the JTAG-DP registers.
  • Page 298 For most register addresses on the SW-DP, different registers are addressed on read and write accesses. In addition, the CTRLSEL bit in the Select Register changes which register is accessed at address 0b01. 12-48 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 299: Table 12-14 Sw-Dp Register Map

    It is at address 0b00 on write operations when the DPnAP bit =1, see Key to illustrations of operations on page 12-22. Access to the Abort Register is not affected by the value of the CTRLSEL bit in the Select Register. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-49...

  • Page 300: Table 12-15 Abort Register Bit Assignments

    Writing b1 to bit [0] of the Abort Register generates a DP abort, causing the current AP transaction to abort. This also terminates the Transaction Counter, if it was active. 12-50 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 301 • For the STICKYORUN flag, you must find which DP or AP transaction caused the overflow. You then have to repeat your transactions from that point. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-51...

  • Page 302: Table 12-16 Identification Code Register Bit Assignments

    Table 12-16 lists the bit functions of the Identification Code Register. Table 12-16 Identification Code Register bit assignments Bits Function Description [31:28] Version Version code. The meaning of this field is Implementation-defined. 12-52 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 303: Table 12-17 Jedec Jep-106 Manufacturer Id Code, With Arm Limited Values

    [11:1] MANUFACTURER JEDEC Manufacturer ID, an 11-bit JEDEC code that identifies the manufacturer of the device. See The JEDEC Manufacturer ID. The ARM default value for this field, shown in Figure 12-21 on page 12-52, is 0x23B Designers can change the value of this field. If the DAP is also used for boundary scan then this field must be set to the JEDEC Manufacturer ID assigned to the implementor.

  • Page 304: Table 12-18 Control/Status Register Bit Assignments

    Debug reset request. After a reset this bit is Low (0). [25:24] Reserved, RAZ/SBZP [21:12] TRNCNT Transaction counter. After a reset the value of this field is Unpredictable. 12-54 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 305 This field sets the transfer mode for AP operations, see Transfer mode (TRNMODE), bits [3:2] on page 12-57. After a reset the value of this field is Unpredictable. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-55...

  • Page 306: Table 12-19 Control Of Pushed Operation Comparisons By Masklane

    Include byte lane 0 in comparisons. 0x------FF a. Bits [11:8] of the CTRL/STAT Register. b. Bytes of the mask shown as -- are determined by the other bits of MASKLANE. 12-56 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 307: Table 12-20 Transfer Mode, Trnmode, Bit Definitions

    Access to the AP Select Register is not affected by the value of the CTRLSEL bit. Figure 12-23 on page 12-58 shows the register bit assignments. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-57...

  • Page 308: Table 12-21 Bit Assignments For The Ap Select Register, Select

    If APSEL is set to a non-existent AP then all AP transactions return zero on reads and are ignored on writes. Note Every ARM Debug Interface implementation must include at least one AP. 12-58 Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 309: Table 12-22 Ctrlsel Field Bit Definitions

    AP access. After you have read the Read Buffer, its contents are no longer valid. The result of a second read of the Read Buffer is Unpredictable. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-59...

  • Page 310: Figure 12-24 Bit Assignments For The Wire Control Register (Sw-Dp Only)

    Many features of the Wire Control Register are Implementation-defined. Figure 12-24 shows the register bit assignments. Figure 12-24 Bit assignments for the Wire Control Register (SW-DP only) 12-60 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 311: Table 12-23 Bit Assignments For The Wire Control Register (Sw-Dp Only)

    3 sample periods. 4 sample periods. a. Bits [9:8] of the WCR Register. Wire operating mode, WIREMODE, bits [7:6] This field identifies SW-DP as operating in Synchronous mode only. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 12-61...

  • Page 312: Table 12-25 Wire Operating Mode, Wiremode, Bit Definitions

    The RESEND register can be accessed multiple times. It always returns the same value until a new access is made to the DP RDBUFF register or to an AP register. 12-62 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 313 This chapter describes the Trace Port Interface Unit (TPIU). It contains the following sections: • About the Trace Port Interface Unit on page 13-2 • TPIU registers on page 13-8. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 13-1...

  • Page 314: About The Trace Port Interface Unit

    A configuration that supports both ITM and ETM debug trace. Note If your Cortex-M3 system uses the optional ETM component, you must use the TPIU configuration that supports both ITM and ETM debug trace. For a full description of the ETM, see Chapter 15 Embedded Trace Macrocell.

  • Page 315: Figure 13-1 Block Diagram Of The Tpiu (Non-Etm Version)

    Trace Port Interface Unit Figure 13-1 Block diagram of the TPIU (non-ETM version) ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 13-3...

  • Page 316: Figure 13-2 Block Diagram Of The Tpiu (Etm Version)

    APB interface on page 13-5. Asynchronous FIFO The asynchronous FIFO enables trace data to be driven out at a speed that is not dependent on the speed of the core clock. 13-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 317: Table 13-1 Trace Out Port Signals

    Data changes on the rising edge only. TRESETn Input This is a reset signal for the TRACECLKIN domain. This signal is typically driven from Power on Reset, and should be synchronized to TRACECLKIN. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 13-5...

  • Page 318: Table 13-2 Atb Port Signals

    Trace data input from source 2. ATID2S[6:0] Input Trace source ID for source 2. This must not change dynamically. Miscellaneous configuration inputs Table 13-3 on page 13-7 describes the miscellaneous configuration inputs. 13-6 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 319: Table 13-3 Miscellaneous Configuration Inputs

    Defines the maximum number of pins available for synchronous trace output. [1:0] SyncReq Input Global trace synchronization trigger. Used to insert synchronization packets into the formatted data stream. Not used for non-ETM configurations. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 13-7...

  • Page 320: Table 13-4 Tpiu Registers

    TPA. The value on MAXPORTSIZE causes bits within the Supported Port Size register that represent wider widths to be clear, that is, unsupported. 13-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 321: Table 13-5 Current Output Speed Divisors Register Bit Assignments

    Table 13-5 describes the fields of the Current Output Speed Divisors Register. Table 13-5 Current Output Speed Divisors Register bit assignments Field Name Definition [31:13] Reserved. RAZ/SBZP [12:0] PRESCALER Divisor for TRACECLKIN is Prescaler + 1 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 13-9...

  • Page 322: Table 13-6 Selected Pin Protocol Register Bit Assignments

    Use the Formatter and Flush Status Register to read the status of TPIU formatter. The register address, access type, and Reset state are: Address 0xE0040300 Access Read only Reset state 0x08 13-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 323: Table 13-7 Formatter And Flush Status Register Bit Assignments

    0x102 Formatter Synchronization Counter Register The global synchronization trigger is generated by the PC Sampler block. This means that there is no synchronization counter in the TPIU. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 13-11...

  • Page 324: Table 13-8 Integration Test Register Bit Assignments

    Use the Integration Test Registers to perform topology detection of the TPIU with other devices in a Cortex-M3 system. These registers enable direct control of outputs and the ability to read the value of inputs. The processor provides two Integration Test Registers: •...

  • Page 325: Table 13-9 Integration Test Register Bit Assignments

    Table 13-9 describes the fields of the Integration Test Register bit assignments. Table 13-9 Integration Test Register bit assignments Field Name Definition [31:1] Reserved ATVALID1, ATVALID2 This bit reads or sets the value of ATVALIDS1 OR-ed with ATVALIDS2. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 13-13...
  • Page 326 Trace Port Interface Unit 13-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 327 • Access alignment on page 14-9 • Unaligned accesses that cross regions on page 14-10 • Bit-band accesses on page 14-11 • Write buffer on page 14-12. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 14-1...

  • Page 328: About Bus Interfaces

    The processor contains an internal Private Peripheral Bus for accesses to the Nested Vectored Interrupt Controller (NVIC), Data Watchpoint and Trigger (DWT), Flash Patch and Breakpoint (FPB), and Memory Protection Unit (MPU). 14-2 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 329: Table 14-1 Instruction Fetches

    If an MPU is fitted, the MPU region attributes are ignored for the ICode bus. HPROTI[0] indicates what is being fetched: • 0 - instruction fetch • 1 - vector fetch. All ICode transactions are performed as non-sequentials. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 14-3...
  • Page 330 This can be used, for example, by a prefetcher to prevent prefetching if a branch is about to be fetched. For more information about the branch status signal, see Chapter 16 Embedded Trace Macrocell Interface. 14-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 331: Dcode Bus Interface

    Memory attributes The processor exports memory attributes on the DCode bus by using a sideband bus called MEMATTRD. For more information, see Memory attributes on page 14-13. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 14-5...

  • Page 332: System Interface

    The System bus supports exclusive accesses. This is carried out using two sideband signals, EXREQS and EXRESPS. For more information, see System bus interface on page A-8. 14-6 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 333 System bus are not possible. Note Instruction fetch requests to the ICode bus are not registered. Performance critical code should be run from the ICode interface. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 14-7...

  • Page 334: External Private Peripheral Interface

    Unaligned accesses to this bus are architecturally unpredictable and not supported. The processor drives out the original HADDR[1:0] request from the core and does not convert the request into multiple aligned accesses. 14-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 335: Table 14-2 Bus Mapper Unaligned Accesses

    Bus Interface 14.6 Access alignment The Cortex-M3 processor supports unaligned data accesses using the ARMv6 model. The DCode and System bus interfaces contain logic that converts unaligned accesses to aligned accesses. The unaligned data accesses are described in Table 14-2. The table shows the unaligned access in the first column, with the remaining columns showing what the access is converted into.

  • Page 336: Unaligned Accesses That Cross Regions

    (the first byte of the bit-band alias). 0x22000000 Unaligned loads that match against a literal comparator in the FPB are not remapped. FPB only remaps aligned addresses. 14-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 337: Bit-Band Accesses

    System bus while the bit-band operation is being carried out. • Big endian accesses to the bit-band alias region must be byte-sized. Otherwise, the accesses are unpredictable. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 14-11...

  • Page 338: Write Buffer

    14.9 Write buffer To prevent bus wait cycles from stalling the Cortex-M3 processor during data stores, buffered stores to the DCode and System buses go through a one-entry write buffer. If the write buffer is full, subsequent accesses to the bus stall until the write buffer has drained.

  • Page 339: Table 14-3 Memory Attributes

    Strongly ordered Device L1 cacheable, L2 not cacheable Invalid Invalid Cache WT, allocate on read Cache WB, allocate on read and write Cache WB, allocate on read ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 14-13...
  • Page 340 Bus Interface 14-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 341 Data tracing on page 15-6 • ETM Resources on page 15-7 • Trace output on page 15-9 • ETM architecture on page 15-10 • ETM programmer’s model on page 15-14. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-1...

  • Page 342: About The Etm

    ETM block diagram Figure 15-1 on page 15-3 shows a block diagram of the ETM, and shows how the ETM interfaces to the Trace Port Interface Unit (TPIU) block. 15-2 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 343: Figure 15-1 Etm Block Diagram

    Embedded Trace Macrocell Figure 15-1 ETM block diagram ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-3...

  • Page 344: Table 15-1 Cortex-M3 Resources

    Branch broadcasting ASIC Control Register Data suppression Software access to registers Readable registers FIFO size 16 bytes Minimum port size 8 bytes Maximum port size 8 bytes 15-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 345 Mux port mode/2:1 1:4 port mode Dynamic port mode (including stalling) No. Supported by asynchronous port mode. CPRT data Load PC first Fetch comparisons Load data traced ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-5...

  • Page 346: Data Tracing

    15.2 Data tracing The Cortex-M3 system can perform low-bandwidth data tracing using the Data Watchpoint and Trace (DWT) and Instruction Trace Macrocell (ITM) components. To enable instruction trace to be supported with a low pin-count, data trace is not included in the ETM.

  • Page 347: Etm Resources

    See Data Watchpoint and Trace on page 11-12 for more information about the DWT unit. External inputs Two external inputs, ETMEXTIN[1:0], enable additional on-chip IP to generate trigger/enable signals for the ETM. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-7...
  • Page 348 Although stalling the core in a typical application is unlikely to be acceptable, it provides a mechanism for enabling 100% trace which could be compared with the partial trace obtained for a non-stalled run. 15-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 349: Trace Output

    ETM FIFO. However, with an 8-bit ATB port the FIFO always drains which makes AFVALID unnecessary. The Cortex-M3 system is equipped with an optimized TPIU that is designed for use with the ETM and ITM. This TPIU does not support additional trace sources. However, additional trace sources can be added if the TPIU has been replaced with a more complex version, and more trace infrastructure.

  • Page 350: Figure 15-2 Exception Return Packet Encoding

    Embedded Trace Macrocell 15.5 ETM architecture The ETM is an instruction only ETM that implements ARM ETM architecture v3.4. It is based on the ARM ETM Architecture specification. For full details, see the ARM Embedded Trace Macrocell Architecture Specification. All Thumb-2 instructions are traced as a single instruction. Instructions following an IT instruction are traced as normal conditional instructions.

  • Page 351: Table 15-2 Exception Tracing Mapping

    1 byte exception SysTick 2 bytes exception Reserved 2 bytes exception Reset 2 bytes exception Reserved 2 bytes exception HardFault 2 bytes exception Reserved 2 bytes exception BusFault ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-11...

  • Page 352: Figure 15-3 Exception Encoding For Branch Packet

    2 bytes exception IRQ10 2 bytes exception IRQ239 The full branch with exception packet is shown in Figure 15-3 on page 15-12. Figure 15-3 Exception encoding for branch packet 15-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 353 When turning off trace immediately before entry to an exception handler, the ETM remains enabled until the exception is taken. This enables it to trace the branch address, exception type and resume information. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-13...

  • Page 354: Table 15-3 Etm Registers

    SW-DP/JTAG-DP. 15.6.2 List of ETM registers The ETM registers are listed in Table 15-3. For full details, see the ARM Embedded Trace Macrocell Architecture Specification. Table 15-3 ETM registers...
  • Page 355 Implemented as normal. 0xE0041304- OS Save/Restore OS Save/Restore not 0xE0041308 implemented. RAZ, ignore writes. 0xE0041EE0 ITMISCIN Sets [1:0] to EXTIN[1:0], [4] to COREHALT. 0xE0041EE8 ITTRIGOUT Sets [0] to TRIGOUT. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-15...
  • Page 356 15.6.3 Description of ETM registers An additional description of some of the ETM registers is given in the following sections. For full details, see the ARM Embedded Trace Macrocell Architecture Specification. 15-16 Copyright © 2005, 2006 ARM Limited. All rights reserved.
  • Page 357 Bits 11:10 are implemented as normal. Bits 9, 2:0 are fixed as 4’b0001. TraceEnable Control 1 Register The TraceEnable Control 1 Register is one of the registers that configures TraceEnable. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 15-17...
  • Page 358 • start/stop block uses E-ICE inputs • four embedded ICE inputs • no data comparisons supported • all registers are readable • no extended external input supported. 15-18 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 359 This chapter describes the Embedded Trace Macrocell (ETM) interface. It contains the following sections: • About the ETM interface on page 16-2 • CPU ETM interface port descriptions on page 16-3 • Branch status interface on page 16-5. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 16-1...

  • Page 360: About The Etm Interface

    16.1 About the ETM interface The ETM interface enables simple connection of an ETM to the processor. It provides a channel for instruction trace to the ETM. 16-2 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 361: Table 16-1 Etm Interface Ports

    ETMINTSTAT Entry/Return is asserted in the first cycle of the new interrupt context. Exit occurs without ETMIVALID. ETMINTNUM[8:0] Output ETMINTSTAT Interrupt number. Marks the interrupt number of the current execution context. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 16-3...
  • Page 362 Current opcode in execute has been cancelled. Opcodes that are interrupted restart or continue on return to this execution context. These include: LDR/STR LDRD/STRD LDM/STM U/SMULL U/SDIV CPSID 16-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 363: Figure 16-1 Conditional Branch Backwards Not Taken

    Note HADDRICore and HTRANSICore are the address and transaction request signals from the processor, and not the signals on the external Cortex-M3 interface. Figure 16-3 on page 16-6 and Figure 16-4 on page 16-6 show a conditional branch forwards not taken and taken. The branch occurs speculatively in the decode phase of the opcode.

  • Page 364: Figure 16-3 Conditional Branch Forwards Not Taken

    The branch occurs in the decode phase of the opcode. The branch target is an aligned 32-bit opcode. Figure 16-5 Unconditional branch without pipeline stalls 16-6 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 365: Figure 16-6 Unconditional Branch With Pipeline Stalls

    The branch target is an aligned and unaligned 32-bit ALU opcode. Figure 16-7 Unconditional branch in execute aligned Figure 16-8 Unconditional branch in execute unaligned ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 16-7...
  • Page 366 Embedded Trace Macrocell Interface 16-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 367 This chapter describes the instruction timings of the processor. It contains the following sections: • About instruction timing on page 17-2 • Processor instruction timings on page 17-3 • Load-store timings on page 17-7 ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 17-1...

  • Page 368: About Instruction Timing

    Every instruction must be fetched and every load/store must go out to the system. These factors are discussed here along with intended system design (and the implications for timing). 17-2 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 369: Table 17-1 Instruction Timings

    ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S}, 1 (+P if PC is destination) with 3 register CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S}, MOV{S}, ORN{S}, and MVN{S}. No PKxxx instructions. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 17-3...
  • Page 370 System CPSIE and CPSID are quick versions of MSR(2) instructions and use the standard Thumb-2 encodings, but only allow use of "i" and "f" and not "a". 17-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 371 1 cycle of pipeline reload (2 cycles total). Taken branches with register operand are normally 2 cycles of pipeline reload (3 cycles total). Pipeline reload is longer when branching to unaligned 32-bit instructions as well ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 17-5...
  • Page 372 ISB takes one cycle (acts as branch). DMB and DSB will take one cycle unless data is pending in the write buffer or LSU. If an interrupt comes in during a barrier, it will be abandoned/restarted. 17-6 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 373: Load-Store Timings

    LDR, but nothing may be pipelined after the store. Even a stalled STR will normally only take two cycles, because of the store buffer (used for bit band, data ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. 17-7...
  • Page 374 These numbers will be increased if the memory stalls. A STR or STRH may not delay the processor due to the store buffer. 17-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 375 Private Peripheral Bus interface on page A-9 • ITM interface on page A-10 • AHB-AP interface on page A-11 • ETM interface on page A-12 • Test interface on page A-13. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 376: Table A-1 Clock Signals

    Clocks Table A-1 lists the clock signals. Table A-1 Clock signals Name Direction Description HCLK Input Main Cortex-M3 clock FCLK Input Free-running Cortex-M3 clock DAPCLK Input AHB-AP clock Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 377: Table A-2 Reset Signals

    SYSRESETn Input System reset. Resets processor, non-debug portion of NVIC, Bus Matrix, and MPU. Debug components are not reset. SYSRESETREQ Output System reset request. DAPRESETn Input AHB-AP reset. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 378: Table A-3 Miscellaneous Signals

    Description LOCKUP Output Indicates that the core is locked up. SLEEPDEEP Output Indicates that the Cortex-M3 clock can be stopped. SLEEPING Output Indicates that the Cortex-M3 clock can be stopped. CURRPRI[7:0] Output Indicates what priority interrupt (or base boost) is currently used. CURRPRI represents the pre-emption priority, and does not indicate the secondary priority.

  • Page 379: Table A-4 Interrupt Interface

    Interrupt interface Table A-4 lists the signals of the external interrupt interface. Table A-4 Interrupt interface Name Direction Description INTISR[239:0] Input External interrupt signals INTNMI Input Non-maskable interrupt ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 380: Table A-5 Icode Interface

    When HIGH indicates that a transfer has completed on the bus. This signal is driven LOW to extend a transfer. HRESPI[1:0] Input The transfer response status. OKAY or ERROR. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 381: Table A-6 Dcode Interface

    When HIGH indicates that a transfer has completed on the bus. This signal is driven LOW to extend a transfer. HRESPD[1:0] Input The transfer response status. OKAY or ERROR. HRDATAD[31:0] Input Read data. EXRESPD Input Exclusive response. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 382: Table A-7 System Bus Interface

    When HIGH indicates that a transfer has completed on the bus. The signal is driven LOW to extend a transfer. HRESPS[1:0] Input The transfer response status. OKAY or ERROR. EXRESPS Input Exclusive response. Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 383: Table A-8 Private Peripheral Bus Interface

    Strobe to time all accesses. Used to indicate the second cycle of an APB transfer. PWDATA[31:0] Output 32-bit write data bus. PWRITE Output Write not read. PRDATA[31:0] Input Read data bus. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.

  • Page 384: Table A-9 Itm Interface

    Table A-9 ITM interface Name Direction Description ATVALID Output ATB valid AFREADY Output ATB flush ATDATA[7:0] Output ATB data ATIDITM[6:0] Output ITM ID for TPIU ATREADY Input ATB ready A-10 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 385: Table A-10 Ahb-Ap Interface

    The write bus is driven by the DP block during write cycles (when DAPWRITE is HIGH). DAPABORT Input Aborts the current transfer. The AHB-AP returns DAPREADY HIGH without affecting the state of the transfer in progress in the AHB Master Port. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. A-11...

  • Page 386: Table A-11 Etm Interface

    Opcode fold. An IT or NOP opcode has been folded in this cycle. PC advances past the current (16-bit) opcode plus the IT/NOP instruction (16 bits). This is reflected in the ETMIA. DSYNC Synchronization pulse from DWT. A-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

  • Page 387: Table A-12 Test Interface

    Table A-12 lists the signals of the Test interface. Table A-12 Test interface Name Direction Description Input Scan enable. RSTBYPASS Input Reset bypass for scan testing. PORESETn is the only reset used during scan testing. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. A-13...
  • Page 388 Signal Descriptions A-14 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 389 Glossary This glossary describes some of the terms used in technical documents from ARM Limited. A mechanism that indicates to a core that the attempted memory access is invalid or not Abort allowed or that the data returned by the memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid or protected instruction or data memory.
  • Page 390 A family of protocol specifications that describe a strategy for the interconnect. AMBA is the ARM open standard for on-chip buses. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
  • Page 391 An instruction of the ARM Instruction Set Architecture (ISA). These cannot be ARM instruction executed by the Cortex-M3. The processor state in which the processor executes the instructions of the ARM ISA. ARM state The processor only operates in Thumb state, never in ARM state.
  • Page 392 Glossary-4 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 393 Glossary The ARM architecture supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is selected, unaligned halfword and word memory accesses are also supported. Multi-word accesses are expected to be word-aligned. See also Word-invariant. Gating a clock signal for a macrocell with a control signal and using the modified clock Clock gating that results to control the operating state of the macrocell.
  • Page 394 The formatter is an internal input block in the ETB and TPIU that embeds the trace Formatter source ID within the data to create a single trace stream. A 16-bit data item. Halfword Glossary-6 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 395 The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG. See Joint Test Action Group. JTAG ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. Glossary-7...
  • Page 396 Memory Protection Unit (MPU) Hardware that controls access permissions to blocks of memory. Unlike an MMU, an MPU does not modify addresses. See Processor. Microprocessor Glossary-8 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...
  • Page 397 These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as 0. ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved. Glossary-9...
  • Page 398 TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores because it is used to reset the debug logic. A halfword that specifies an operation for an ARM processor in Thumb state to Thumb instruction perform.
  • Page 399 The change of endianness occurs because of the change to the byte addresses, not because the bytes are rearranged. The ARM architecture supports word-invariant systems in ARMv3 and later versions. When word-invariant support is selected, the behavior of load or store instructions that are given unaligned addresses is instruction-specific, and is in general not the expected behavior for an unaligned access.
  • Page 400 See also Byte-invariant. A pipeline stage for buffering write data to prevent bus stalls from stalling the processor. Write buffer Glossary-12 Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B...

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