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10.2.5
Communication to the Power Management Controller
ARM DDI 0301H
ID012310
•
All CP15 registers are saved, including the DMA state.
•
All VFP registers are saved if the VFP contains defined state.
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Any locked entries in the main TLB are saved.
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All debug-related state are saved.
•
The Master Valid bits for the cache are saved. These are accessed using CP15 register c15
as c15, Instruction Cache Master Valid Register on page 3-147 describes.
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A Data Synchronization Barrier operation is performed to ensure that all state saving has
been completed.
A Wait For Interrupt CP15 operation is executed, enabling the signal STANDBYWFI to
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indicate that the processor can enter Dormant mode.
•
On entry into Dormant mode, the Reset signal to the processor must be asserted by the
external power control mechanism.
Transition from Dormant state to Run state is triggered by the external power controller
asserting Reset to the processor until the power to the processor is restored. When power has
been restored the core leaves reset and, by interrogating the external power controller, can
determine that the saved state must be restored.
Your Power Management Controller in your system must perform the powering up and
powering down of the power domains of the processor. The Power Management Controller must
be a memory-mapped controller. The ARM1176JZF-S processor accesses this controller using
Strongly-Ordered accesses.
The STANDBYWFI signal can also be used to signal to the Power Management Controller that
the ARM1176JZF-S processor is ready to have its power state changed. STANDBYWFI is
asserted in response to a Wait For Interrupt operation.
Note
The Power Management Controller must not power down any of the processor power domains
unless STANDBYWFI is asserted.
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Power Control
10-5
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