Figure 2-7 Processor Core Register Set Showing Banked Registers - ARM ARM1176JZF-S Technical Reference Manual

16 general
purpose
registers + 1
status register
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
CPSR
2.9.2 The Thumb state core register set
ARM DDI 0301H
ID012310
17 banked general-purpose registers + 6 banked status registers
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq R13_svc
R14_fiq R14_svc
SPSR_fiq SPSR_svc

Figure 2-7 Processor core register set showing banked registers

The Thumb state core register set is a subset of the ARM state set. The programmer has direct
access to:
• eight general registers, R0–R7. For details of high register access in Thumb state see
Accessing high registers in Thumb state on page 2-22
• the PC
• a stack pointer, SP, ARM R13
• an LR, ARM R14
• the CPSR.
There are banked SPs, LRs, and SPSRs for each privileged mode. Figure 2-8 on page 2-22
shows the Thumb state core register set.
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23 mode-specific registers (banked registers)
R13_abt R13_irq
R14_abt R14_irq
SPSR_abt SPSR_irq
Programmer's Model
R13_und R13_mon
R14_und R14_mon
SPSR_und SPSR_mon
2-21