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Bits
R/W
Name
[31:25]
-
-
[24]
R/W
TRCENA
[23:20]
-
-
[19]
R/W
MON_REQ
[18]
R/W
MONSTEP
ARM DDI 0337B
Figure 10-3 Debug Exception and Monitor Control Register format
Table 10-4 shows the bit functions of the Debug Exception and Monitor Control
Register.
Function
Reserved, SBZP
This bit must be set to 1 to enable use of the trace and debug blocks:
•
Data Watchpoint and Trace (DWT)
•
Instruction Trace Macrocell (ITM)
•
Embedded Trace Macrocell (ETM)
•
Trace Port Interface Unit (TPIU).
This enables control of power usage unless tracing is required. This can be
enabled by the application, for ITM use, or by a debugger.
Reserved, SBZP
a
This enables the monitor to identify how it wakes up:
1 = woken up by MON_PEND
0 = woken up by debug exception.
a
When MON_EN = 1, this is used to step the core. When MON_EN = 0, this
bit is ignored. This is the equivalent to C_STEP. Interrupts are only stepped
according to the priority of the monitor and settings of PRIMASK,
FAULTMASK, or BASEPRI.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 10-4 Debug Exception and Monitor Control Register
Core Debug
10-9
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