Table 3-143 Results Of Access To The System Validation Counter Register; Figure 3-74 System Validation Counter Register Format For External Debug Request Counter - ARM ARM1176JZF-S Technical Reference Manual

Function
Reset, interrupt, and
fast interrupt counters
External debug request
counter
ARM DDI 0301H
ID012310
31

Figure 3-74 System Validation Counter Register format for external debug request counter

Table 3-143 lists the results of attempted access for each mode. Access in Secure User mode and
in the Non-secure world depends on the V bit, see c15, Secure User and Non-secure Access
Validation Control Register on page 3-132.

Table 3-143 Results of access to the System Validation Counter Register

Secure Privileged
V
bit
Read
0 Data
1 Data
0 Unpredictable
1 Unpredictable
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
To use the System Validation Counter Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c12
• Opcode_2 set to:
— 1, Read/write reset counter
— 2, Read/write interrupt counter
— 3, Read/write fast interrupt counter
— 7, Write external debug request counter.
For example:
MRC p15, 0, <Rd>, c15, c12, 1
MCR p15, 0, <Rd>, c15, c12, 1
MRC p15, 0, <Rd>, c15, c12, 2
MCR p15, 0, <Rd>, c15, c12, 2
MRC p15, 0, <Rd>, c15, c12, 3
MCR p15, 0, <Rd>, c15, c12, 3
MCR p15, 0, <Rd>, c15, c12, 7
A read or write to the System Validation Counter Register with a value of Opcode_2 other than
1, 2, 3, or 7 has no effect.
When the system starts the counters they count up, incrementing by one on each core clock
cycle, until they wrap around. When the counters wrap around they cause the specified event to
occur. See c15, System Validation Operations Register on page 3-142.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
SBZ/UNP
Non-secure Privileged
Write Read Write
Data Undefined Undefined
exception exception
Data Data Data
Data Undefined Undefined
exception exception
Data Unpredictable Data
;Read reset counter
;Write reset counter
;Read interrupt counter
;Write interrupt counter
;Read fast interrupt counter
;Write fast interrupt counter
;Write external debug request counter
System Control Coprocessor
6 5 0
Counter value
User
Read Write
Undefined Undefined
exception exception
Data Data
Undefined Undefined
exception exception
Unpredictable Data
3-141