16.15 Coprocessor Instructions; Table 16-22 Coprocessor Instructions Cycle Timing Behavior - ARM ARM1176JZF-S Technical Reference Manual

16.15 Coprocessor instructions

ARM DDI 0301H
ID012310
This section describes the cycle timing behavior for the CDP, LDC, STC, LDCL, STCL, MCR,
MRC, MCRR, and MRRC instructions.
The precise timing of coprocessor instructions is tightly linked with the behavior of the relevant
coprocessor. The numbers in Table 16-22 are best case numbers. For LDC/STC instructions, the
coprocessor can determine how many words are required. Table 16-22 lists the coprocessor
instructions cycle timing behavior.
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Table 16-22 Coprocessor Instructions cycle timing behavior

Cycle
Instruction
s
1
MCR
1
MCRR
1
MRC
1
MRRC
1
LDC/LDCL
1
STC/STCL
1
CDP
Cycle Timings and Interlock Behavior
Memory cycles Result latency
1 -
1 -
1 3
1 3/3
As required -
As required -
1 -
16-25