Table 3-118 Results Of Access To The Dma Channel Status Register - ARM ARM1176JZF-S Technical Reference Manual

U DMA
bit bit
0 0
1
1 0
1
ARM DDI 0301H
ID012310
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. These registers can be accessed in User mode if the U bit, see c11, DMA
User Accessibility Register on page 3-107, for the currently selected channel is set to 1.
Table 3-118 lists the results of attempted access for each mode.

Table 3-118 Results of access to the DMA Channel Status Register

Secure Non-secure
Privileged Privileged
Read Write Read
Data Undefined Undefined
exception exception
Data Undefined Data
exception
Data Undefined Undefined
exception exception
Data Undefined Data
exception
To access the DMA Channel Status Register set DMA Channel Number Register to the
appropriate DMA channel and read CP15 with:
• Opcode_1 set to 0
• CRn set to c11
• CRm set to c8
• Opcode_2 set to 0.
MRC p15, 0, <Rd>, c11, c8, 0
In the event of an error, the appropriate Start Address Register contains the address that faulted,
unless the error is an external error that is set to b11010 by bits [11:7].
A channel with the state of Queued changes to Running automatically if the other channel, if
implemented, changes to Idle, or Complete or Error, with no error.
When a channel completes all of the transfers of the DMA, so that all changes to memory
locations caused by those transfers are visible to other observers, its status is changed from
Running to Complete or Error. This change does not happen before the external accesses from
the transfer complete.
If the processor attempts to access memory locations that are not marked as shared, then the ES
bits signal an Unshared error for either:
• a DMA transfer in User mode
• a DMA transfer that has the UM bit set in the DMA Control Register.
A DMA transfer where the external address is within the range of the TCM also results in an
Unshared data error.
If the DMA channel is configured Secure, in the event of an error the processor asserts the
nDMASIRQ pin provided it is not masked. If the channel is configured Non-secure, in the event
of an error the processor asserts the nDMAIRQ pin, provided it is not masked. In the event of
an external abort on a page table walk caused by the DMA, the processor asserts the
nDMAEXTERRIRQ output.
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Non-Confidential, Unrestricted Access
Secure User
Write Read Write
Undefined Undefined Undefined
exception exception exception
Undefined Undefined Undefined
exception exception exception
Undefined Data Undefined
exception exception
Undefined Data Undefined
exception exception
; Read DMA Channel Status Register
System Control Coprocessor
Non-secure User
Read Write
Undefined Undefined
exception exception
Undefined Undefined
exception exception
Undefined Undefined
exception exception
Data Undefined
exception
3-119