Table 20-6 Encoding Of The Floating-Point Status And Control Register - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 20-6 lists the FPSCR bit fields.

Table 20-6 Encoding of the Floating-Point Status and Control Register

Bits Name
[31] N
[30] Z
[29] C
[28] V
[27:26] -
[25] DN
[24] FZ
[23:22] Rmode
[21:20] Stride
[19] -
[18:16] LEN
[15] IDE
[14:13] -
[12] IXE
[11] UFE
[10] OFE
[9] DZE
[8] IOE
[7] IDC
[6:5] -
[4] IXC
[3] UFC
[2] OFC
[1] DZC
[0] IOC
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Meaning
Set if comparison produces a less than result
Set if comparison produces an equal result
Set if comparison produces an equal, greater than, or unordered result
Set if comparison produces an unordered result
Should Be Zero
Default NaN mode enable bit:
1 = default NaN mode enabled
0 = default NaN mode disabled
Flush-to-zero mode enable bit:
1 = flush-to-zero mode enabled
0 = flush-to-zero mode disabled
Rounding mode control field:
b00 = Round to nearest (RN) mode
b01 = Round towards plus infinity (RP) mode
b10 = Round towards minus infinity (RM) mode
b11 = Round towards zero (RZ) mode
See Vector length and stride control on page 20-16
Should Be Zero
See Vector length and stride control on page 20-16
Input Subnormal exception trap enable bit
Should Be Zero
Inexact exception trap enable bit
Underflow exception trap enable bit
Overflow exception trap enable bit
Division by Zero exception trap enable bit
Invalid Operation exception trap enable bit
Input Subnormal cumulative exception flag
Should Be Zero
Inexact cumulative exception flag
Underflow cumulative exception flag
Overflow cumulative exception flag
Division by Zero cumulative exception flag
Invalid Operation cumulative exception flag
VFP Programmer's Model
20-15