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18.5
Modes of operation
18.5.1
Full-compliance mode
ARM DDI 0301H
ID012310
The VFP11 coprocessor provides compatibility with the IEEE 754 standard through a
combination of hardware and software. There are rare cases that require significant additional
compute time to resolve correctly according to the requirements of the IEEE 754 standard. For
instance, the VFP11 coprocessor does not process subnormal input values directly. To provide
correct handling of subnormal inputs according to the IEEE 754 standard, a trap is made to
support code to process the operation. Using the support code for processing this operation can
require hundreds of cycles. In some applications this is unavoidable, because compliance with
the IEEE 754 standard is essential to proper operation of the program. In many other
applications, strict compliance to the IEEE 754 standard is unnecessary, while determinable
runtime, low interrupt latency, and low power are of more importance. To accommodate a
variety of applications, the VFP11 coprocessor provides four modes of operation:
•
Full-compliance mode
•
Flush-to-zero mode on page 18-12
•
Default NaN mode on page 18-12
•
RunFast mode on page 18-12.
When the VFP11 coprocessor is in full-compliance mode, all operations that cannot be
processed according to the IEEE 754 standard use support code for assistance. The operations
requiring support code are:
•
Any CDP operation involving a subnormal input when not in flush-to-zero mode. Enable
flush-to-zero mode by setting the FZ bit, FPSCR[24].
•
Any CDP operation involving a NaN input when not in default NaN mode. Enable default
NaN mode by setting the DN bit, FPSCR[25].
•
Any CDP operation that has the potential of generating an underflow condition when not
in flush-to-zero mode.
•
Any CDP operation when Inexact exceptions are enabled. Enable Inexact exceptions by
setting the IXE bit, FPSCR[12].
•
Any CDP operation that can cause an overflow while Overflow exceptions are enabled.
Enable Overflow exceptions by setting the OFE bit, FPSCR[10].
•
Any CDP operation that involves an invalid arithmetic operation or an arithmetic
operation on a signaling NaN when Invalid Operation exceptions are enabled. Enable
Invalid Operation exceptions by setting the IOE bit, FPSCR[8].
•
A float-to-integer conversion that has the potential to create an integer that cannot be
represented in the destination integer format when Invalid Operation exceptions are
enabled.
The support code:
•
determines the nature of the exception
•
determines if processing is required to perform the computation
•
calls a function to compute the result and status
•
transfers control to the user trap handler if the enable bit is set for a detected exception
•
writes the result to the destination register, updates the FPSCR register, and returns to the
user code if no enabled exception is detected
•
passes control to the user trap handler and supplies any specified intermediate result for
the exception if an enabled exception is detected.
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Introduction to the VFP coprocessor
18-11
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