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ARM DDI 0301H
ID012310
•
debug in Non-secure only.
The debug coprocessor, CP14, implements a full range of debug features that Chapter 13 Debug
and Chapter 14 Debug Test Access Port describe.
The core provides extensive support for real-time debug and performance profiling.
The following sections describe debug in more detail:
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System performance monitoring
•
ETM interface
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ETM trace buffer
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Software access to trace buffer
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Real-time debug facilities on page 1-19
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Debug and trace Environment on page 1-19.
System performance monitoring
This is a group of counters that you can configure to monitor the operation of the processor and
memory system. See System performance monitor on page 3-10 for more details.
ETM interface
You can connect an external Embedded Trace Macrocell (ETM) unit to the processor for
real-time code tracing of the core in an embedded system.
The ETM interface collects various processor signals and drives these signals from the core. The
interface is unidirectional and runs at the full speed of the core. The ETM interface connects
directly to the external ETM unit without any additional glue logic. You can disable the ETM
interface for power saving.
For more information see:
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the Embedded Trace Macrocell Architecture Specification
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Chapter 15 Trace Interface Port
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Appendix A Signal Descriptions, for details of ETM-related signals.
ETM trace buffer
You can extend the functionality of the ETM by adding an on-chip trace buffer. The trace buffer
is an on-chip memory area. The trace buffer stores trace information during capture that
otherwise passes immediately through the trace port at the operating frequency of the core.
When capture is complete the stored information can be read out at a reduced clock rate from
the trace buffer using the JTAG port of the SoC, instead of through a dedicated trace port.
This is a two-step process that avoids you implementing a wide trace port that has many
high-speed device pins. In effect, a zero-pin trace port is created where the device already has a
JTAG port and associated pins.
Software access to trace buffer
You can access buffered trace information through an APB slave-based memory-mapped
peripheral included as part of the trace buffer. You can perform internal diagnostics on a closed
system where a JTAG port is not normally brought out.
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Introduction
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