Table 3-42 Auxiliary Control Register Bit Functions; Figure 3-27 Auxiliary Control Register Format - ARM ARM1176JZF-S Technical Reference Manual

Field
Bits
name
[31] FIO
[30] FSD
[29] BFD
[28] PHD
[27:7] -
[6] CZ
[5] RV
ARM DDI 0301H
ID012310
The Auxiliary Control Register is:
• in CP15 c1
• a 32-bit:
— read/write register in the Secure world
— read only register in the Non-secure world
• accessible in privileged modes only.
Figure 3-27 shows the arrangement of bits in the register.
31 30 29 28 27
F F B P
I S F H
O D D D
Table 3-42 lists how the bit values correspond with the Auxiliary Control Register functions.
Function
Provides additional level of control for low interrupt latency configuration. This bit overrides the FI
bit, see FI bit in c1, Control Register on page 3-44:
0 = Normal operation for low interrupt latency configuration, reset value
1 = Low interrupt latency configuration overridden. This feature:
• disables the fast interrupt response introduced by setting the FI bit
• disables Hit-Under-Miss (HUM) functionality
• abandons restartable external accesses so that all external aborts to loads are precise.
Provides additional level of control for speculative operations, see c1, Control Register on page 3-44.
Force speculative operations force the PC to a new value because of static, speculative, branch
prediction:
0 = Enable force speculative operations, reset value
1 = Disable force speculative operations.
Disables branch folding. This behavior also depends on the SB and DB bits, [2:1] in this register, and
the Z bit, see c1, Control Register on page 3-44:
0 = Branch folding is enabled, when branch prediction is enabled, reset value
1 = Branch folding is disabled.
Disables instruction prefetch halting on unconditional, unpredictable instructions that later result in a
prefetch buffer flush. This prefetch halting is a power saving technique:
0 = Prefetch halting is enabled, reset value
1 = Prefetch halting is disabled.
UNP/SBZ
Controls the restriction of cache size to 16KB. This enables the processor to run software that does not
support ARMv6 page coloring. When set the CZ bit does not effect the Cache Type Register. See
Restrictions on page table mappings page coloring on page 6-41 for more information:
0 = Normal ARMv6 cache behavior, reset value
1 = Cache size limited to 16KB.
Disables block transfer cache operations:
0 = Block transfer cache operations enabled, reset value
1 = Block transfer cache operations disabled.
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SBZ/UNP

Figure 3-27 Auxiliary Control Register format

Table 3-42 Auxiliary Control Register bit functions

System Control Coprocessor
7 6 5 4 3 2 1 0
C R R T S D R
Z V A R B B S
3-49