ARM Cortex A9 Multi-core Processor Manuals

ARM Cortex A9 Multi-core Processor Manuals

Manuals and User Guides for ARM Cortex A9 Multi-core Processor. We have 1 ARM Cortex A9 Multi-core Processor manual available for free PDF download: Technical Reference Manual

ARM Cortex A9 Technical Reference Manual

ARM Cortex A9 Technical Reference Manual (213 pages)

Brand: ARM | Category: Computer Hardware | Size: 1 MB

Table of Contents

Table of Contents
3
Preface

7
- About this Book
  7
- Timing Diagrams
  9
- Feedback
  11
Chapter 1 Introduction

13
- About the Cortex-A9 Processor
  13
- Cortex-A9 Variants
  15
- Compliance
  16
- Features
  17
- Interfaces
  18
- Configurable Options
  19
- Test Features
  20
- Product Documentation and Design Flow
  21
- Product Revisions
  23
Chapter 2 Functional Description

26
- About the Functions
  26
- Interfaces
  28
- Clocking and Resets
  30
- Power Management
  34
- Constraints and Limitations of Use
  39
Chapter 3 Programmers Model

41
- About the Programmers Model
  41
- Thumbee Architecture
  42
- The Jazelle Extension
  43
- Advanced SIMD Architecture
  44
- Security Extensions Architecture
  45
- Multiprocessing Extensions
  46
- Modes of Operation and Execution
  47
- Memory Model
  48
- Addresses in the Cortex-A9 Processor
  49
Chapter 4 System Control

50
- About System Control
  51
- Register Summary
  52
- Register Descriptions
  67
- Power Control Register
  90
- About Coprocessor CP14
  96
- CP14 Jazelle Register Summary
  97
- CP14 Jazelle Register Descriptions
  98
Chapter 5 Jazelle DBX Registers

105
Chapter 6 Memory Management Unit

105
- About the MMU
  105
- System Control Coprocessor
  106
- TLB Organization
  107
- Memory Access Sequence
  109
- MMU Enabling or Disabling
  110
- External Aborts
  111
Chapter 7 Level 1 Memory System

113
- About the L1 Memory System
  113
- Security Extensions Support
  115
- About the L1 Instruction Side Memory System
  116
- About the L1 Data Side Memory System
  119
- About DSB
  121
- Data Prefetching
  122
- Parity Error Support
  123
- About the Cortex-A9 L2 Interface
  126
- Optimized Accesses to the L2 Memory Interface
  131
- STRT Instructions
  133
Chapter 8 Level 2 Memory Interface

135
Chapter 9 Preload Engine

135
- About the Preload Engine
  135
- PLE Control Register Descriptions
  136
- PLE Operations
  137
Chapter 10 Debug

140
- Debug Systems
  141
- About the Cortex-A9 Debug Interface
  142
- Debug Register Features
  143
- Debug Register Summary
  144
- Debug Register Descriptions
  146
- Debug Management Registers
  152
- Debug Events
  154
- External Debug Interface
  155
Chapter 11 Performance Monitoring Unit

160
- About the Performance Monitoring Unit
  160
- PMU Register Summary
  161
- PMU Management Registers
  163
- Peripheral Identification Registers
  163
- Performance Monitoring Events
  165
Appendix A Signal Descriptions

171
- Clock Signals
  171
- A.1 Clock Signals
  171
- Reset Signals
  172
- A.2 Reset Signals
  172
- Interrupts
  173
- A.3 Interrupts
  173
- Configuration Signals
  174
- A.4 Configuration Signals
  174
- WFE and WFI Standby Signals
  175
- Power Management Signals
  176
- AXI Interfaces
  177
- A.7 AXI Interfaces
  177
- Performance Monitoring Signals
  183
- Exception Flags Signal
  186
- Parity Signal
  187
- A.10 Parity Signal
  187
- MBIST Interface
  188
- A.11 MBIST Interface
  188
- Scan Test Signal
  189
- External Debug Interface
  190
- PTM Interface Signals
  193
Appendix B Cycle Timings and Interlock Behavior

197
- About Instruction Cycle Timing
  197
- Data-Processing Instructions
  198
- Load and Store Instructions
  199
- Multiplication Instructions
  202
- B.4 Multiplication Instructions
  202
- Branch Instructions
  203
- B.5 Branch Instructions
  203
- Serializing Instructions
  204
- B.6 Serializing Instructions
  204
Appendix C Revisions

205

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