Table 3-87 Instruction Tcm Region Register Bit Functions - ARM ARM1176JZF-S Technical Reference Manual

Field
Bits
name
[31:12] Base
address
[11:7] -
[6:2] Size
[1] -
[0] En
a. On writes this field is ignored. For more details see Tightly-coupled memory on page 7-7.
ARM DDI 0301H
ID012310
Table 3-87 lists how the bit values correspond with the Instruction TCM Region Register
functions.
Function
Contains the physical base address of the TCM. The base address must be aligned to the size of the
TCM. Any bits in the range [(log
The base address is 0 at Reset.
UNP/SBZ.
Indicates the size of the TCM on reads
b00000 = 0KB
b00011 = 4KB
b00100 = 8KB
b00101 = 16KB
b00110 = 32KB.
UNP/SBZ.
Indicates if the TCM is enabled:
0 = TCM disabled.
1 = TCM enabled.
The reset value of this bit depends on the value of the INITRAM static configuration signal. If
INITRAM is HIGH then this bit resets to 1. If INITRAM is LOW then this bit resets to 0. For more
information see Static configuration signals on page A-4.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
The value of the En bit at Reset depends on the INITRAM signal:
INITRAM LOW sets En to 0
•
INITRAM HIGH sets En to 1.
•
When INITRAM is HIGH this enables the Instruction TCM directly from reset, with a Base
address of . When the processor comes out of reset, it executes the instructions in the
0x00000
Instruction TCM instead of fetching instructions from external memory, except when the
processor uses high vectors.
Note
When the NS access bit is 0 for Instruction TCM, see c9, Instruction TCM Non-secure Control
Access Register on page 3-94, attempts to access the Instruction TCM Region Register from the
Non-secure world cause an Undefined exception.
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Table 3-87 Instruction TCM Region Register bit functions

(RAMSize)-1):12] are ignored.
2
a
. All other values are reserved:
System Control Coprocessor
3-92