ARM ARM1176JZF-S Technical Reference Manual page 747

CDP instruction
Clean
Clock gating
Clocks Per Instruction (CPI)
Coherency
Cold reset
Communications channel
Condition field
Conditional execution
Context
Control bits
Coprocessor
Copy back
Core
Core reset
CPI
ARM DDI 0301H
ID012310
Coprocessor data processing instruction. For the VFP11 coprocessor, CDP instructions are
arithmetic instructions and FCPY, FABS, and FNEG.
See also Arithmetic instruction.
A cache line that has not been modified while it is in the cache is said to be clean. To clean a
cache is to write dirty cache entries into main memory. If a cache line is clean, it is not written
on a cache miss because the next level of memory contains the same data as the cache.
See also Dirty.
Gating a clock signal for a macrocell with a control signal and using the modified clock that
results to control the operating state of the macrocell.
See Cycles Per Instruction (CPI).
See Memory coherency.
Also known as power-on reset. Starting the processor by turning power on. Turning power off
and then back on again clears main memory and many internal settings. Some program failures
can lock up the processor and require a cold reset to enable the system to be used again. In other
cases, only a warm reset is required.
See also Warm reset.
The hardware used for communicating between the software running on the processor, and an
external host, using the debug interface. When this communication is for debug purposes, it is
called the Debug Comms Channel. In an ARMv6 compliant core, the communications channel
includes the Data Transfer Register, some bits of the Data Status and Control Register, and the
external debug interface controller, such as the DBGTAP controller in the case of the JTAG
interface.
A four-bit field in an instruction that specifies a condition under which the instruction can
execute.
If the condition code flags indicate that the corresponding condition is true when the instruction
starts executing, it executes normally. Otherwise, the instruction does nothing.
The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the Physical Address range that it can access in memory and
the associated memory access permissions.
See also Fast context switch.
The bottom eight bits of a Program Status Register (PSR). The control bits change when an
exception arises and can be altered by software only when the processor is in a privileged mode.
A processor that supplements the main processor. It carries out additional functions that the
main processor cannot perform. Usually used for floating-point math calculations, signal
processing, or memory management.
See Write-back.
A core is that part of a processor that contains the ALU, the datapath, the general-purpose
registers, the Program Counter, and the instruction decode and control circuitry.
See Warm reset.
See Cycles per instruction.
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