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8.1.4
DMA
ARM DDI 0301H
ID012310
The level two data-side controller handles:
•
All external access requests from the Load Store Unit, including cache misses, data
Write-Through operations, and Noncacheable data.
•
SWP instructions and semaphore operations. It schedules all reads and writes on the two
interfaces, that are closely related.
The level two data-side controller also handles the Peripheral Interface.
The level two data-side controller contains the Refill and Write-Back engines for the Data
Cache. These make requests through the Load Store Unit for the individual cache operations that
are required. The decoupling involved means that the level two data-side controller contains
some buffering. The write buffer is an integral part of the level two data-side controller.
Data Read/Write Interface
The Data Read/Write Interface performs reads and swap reads. It services the Data Cache on
cache misses, and reads noncacheable locations.
The Data Read/Write Interface performs writes and swap writes. It services the writes out of the
Write Buffer. Multiple writes can be queued up as part of this interface.
Peripheral Interface
The Peripheral Interface is a bidirectional AXI interface that services peripheral devices. In
ARM1176JZF-S processors, the Peripheral Interface is used for peripherals that are private to
the processor, such as the Vectored Interrupt Controller or Watchdog Timer. Accesses to regions
of memory that are marked as Device and Non-Shared are routed to the Peripheral Interface in
preference to the Data Read/Write Interface.
Instruction and DMA accesses are not routed to the Peripheral port.
Unaligned accesses and exclusive accesses are not supported by the peripheral port, because
they are not supported in Device memory. The order that accesses are presented on the
Peripheral Interface, relative to those on the Data Read/Write Interface is not defined, other than
Strongly Ordered accesses. For this reason, the peripheral port is expected to be used to access
a bus or memory system that is not accessible through the Data Read/Write port. See c15,
Peripheral Port Memory Remap Register on page 3-130 to find out how to remap data accesses
to a defined address region to the peripheral port. In some systems, designers might not want to
use the Peripheral port to access locations in memory that are marked in the page tables as
Non-Shared Device. In these cases, you can use the Remap Registers to remap Non-Shared
Device to Shared Device, so causing these accesses to be made using the main system memory
ports.
The DMA is responsible for:
•
Performing all external memory transactions required by the DMA engine, and for
requesting accesses from the Instruction TCM and Data TCM as required.
•
Queuing the DMA channels as required. The DMA Interface contains several registers
that are CP15 registers dedicated for DMA use, see DMA control on page 3-9 for details.
The DMA contains buffering to enable the decoupling of internal and external requests. This is
because of variable latency between internal and external accesses.
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Level Two Interface
8-4
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