Table 1-8 Addressing Mode 2; Table 1-9 Addressing Mode 2P, Post-Indexed Only - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 1-9 summarizes addressing mode 2P, post-indexed only.
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Table 1-8 Addressing mode 2 (continued)
Addressing mode Assembler
Pre-indexed offset -
Immediate offset
[<Rn>], #+/<immed_12>
Zero offset
[<Rn>]
Register offset
[<Rn>, +/-<Rm>]
Scaled register offset
[<Rn>, +/-<Rm>, LSL #<immed_5>]
[<Rn>, +/-<Rm>, LSR #<immed_5>]
[<Rn>, +/-<Rm>, ASR #<immed_5>]
[<Rn>, +/-<Rm>, ROR #<immed_5>]
[<Rn>, +/-<Rm>, RRX]
Post-indexed offset -
Immediate
[<Rn>], #+/-<immed_12>
Zero offset
[<Rn>]
Register offset
[<Rn>], +/-<Rm>
Scaled register offset
[<Rn>], +/-<Rm>, LSL #<immed_5>
[<Rn>], +/-<Rm>, LSR #<immed_5>
[<Rn>], +/-<Rm>, ASR #<immed_5>
[<Rn>], +/-<Rm>, ROR #<immed_5>
[<Rn>], +/-<Rm>, RRX

Table 1-9 Addressing mode 2P, post-indexed only

Addressing mode Assembler
Post-indexed offset -
Immediate offset
[<Rn>], #+/-<immed_12>
Zero offset
[<Rn>]
Register offset
[<Rn>], +/-<Rm>
Scaled register offset
[<Rn>], +/-<Rm>, LSL #<immed_5>
[<Rn>], +/-<Rm>, LSR #<immed_5>
[<Rn>], +/-<Rm>, ASR #<immed_5>
[<Rn>], +/-<Rm>, ROR #<immed_5>
[<Rn>], +/-<Rm>, RRX
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