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Example instruction
LDR pc, [sp, #cns] (!)
LDR pc, [sp], #cns
LDR pc, [sp, #cns] (!)
LDR pc, [sp], #cns
LDR <cond> pc, [sp, #cns] (!)
LDR <cond> pc, [sp], #cn
LDR pc, <addr_md_1cycle>
LDR pc, <addr_md_2cycle>
a. Table 16-15 for an explanation of
Table 16-15 <addr_md_1cycle> and <addr_md_2cycle> LDR example instruction explanation
Example instruction
<addr_md_1cycle>
LDR <Rd>, [<Rn>, #cns] (!)
LDR <Rd>, [<Rn>, <Rm>] (!)
LDR <Rd>, [<Rn>, <Rm>, LSL #2] (!)
LDR <Rd>, [<Rn>], #cns
LDR <Rd>, [<Rn>], <Rm>
LDR <Rd>, [<Rn>], <Rm>, LSL #2
<addr_md_2cycle>
ARM DDI 0301H
ID012310
Table 16-14 lists the cycle timing behavior for loads to the PC.
Cycle
s
4
4
9
9
8
s
8
a
8
a
9
<addr_md_1cycle>
Only cycle times for aligned accesses are given because Unaligned accesses to the PC are not
supported.
The processor includes a three-entry return stack that can predict procedure returns. Any load
to the pc with an immediate offset, and the stack pointer R13 as the base register is considered
a procedure return.
For condition code failing cycle counts, you must use the cycles for the non-PC destination
variants.
Table 16-15 lists the explanation of
page 16-16 and Table 16-14 use.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Table 16-14 Cycle timing behavior for loads to the PC
Memory cycles
Result latency
1
-
1
-
1
-
1
-
1
-
1
-
1
-
2
-
and
<addr_md_2cycle>
.
<addr_md_1cycle>
Early Reg
Comment
If an immediate offset, or a positive register offset with no
<Rn>
shift or shift LSL #2, then one-issue cycle.
<Rn>, <Rm>
<Rn>, <Rm>
<Rn>
<Rn>, <Rm>
<Rn>, <Rm>
Cycle Timings and Interlock Behavior
Comments
Correctly return stack predicted
Correctly return stack predicted
Return stack mispredicted
Return stack mispredicted
Conditional return, or empty
return stack
Conditional return, or empty
return stack
-
-
and
that Table 16-13 on
<addr_md_2cycle>
16-17
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