Table 7-4 Summary Of Data Accesses To Tcm And Caches - ARM ARM1176JZF-S Technical Reference Manual

Data Data
TCM cache
Hit Hit
Hit Hit
Hit Miss
Hit Miss
Miss Hit
ARM DDI 0301H
ID012310
LDR r1, [r3],#4 ; reads an item from D-cache
ADD r4, r0, r1 ; perform some calculation on the loaded data
CMP r1, r5 ; finished yet?
BLT loop
Each iteration of this loop pays the three cycle penalty twice, because the loads
alternate between cache & TCM. This is an extreme example, of course. Because
of hit-under-miss, this 3 cycle penalty might not stall the integer core. If the same
code uses only D-TCM, or only D-cache, each load typically takes one cycle.
This can be important if a performance critical loop operates on two blocks of
data, one in D-TCM and one in main memory, especially if the data is consumed
in small blocks of a byte or word, rather than multiple words per iteration.
So, if you have all of the dhrystone code and data in TCM, you get better
performance than if you have nearly all in TCM.
It is not required for instruction port(s) to be able to access the Data TCM. An attempt to access
addresses in the range covered by a Data TCM from an instruction port does not result in an
access to the Data TCM. In this case, the instruction is fetched from main memory. It is
anticipated that such accesses can result in external aborts in some systems, because the address
range might not be supported in main memory.
Instruction TCMs must not be programmed to the same base address as a Data TCM and, if the
RAMs are of different sizes, the regions in physical memory of the two RAMs must not be
overlapped because the resulting behavior is architecturally Unpredictable. If an access is made
to a location that is covered by both an Instruction TCM and a Data TCM, the access is only to
the Data TCM.
Table 7-4 summarizes the results of data accesses to TCM and the cache. This also embodies
the unexpected hit behavior for the cache that Unexpected hit behavior on page 7-6 describes.
In Table 7-4, the Data Cache can only be hit if the memory location being accessed is marked
as being Cacheable and Not shareable. A hit to the Data TCM and Instruction TCM refers to
hitting an address in the range covered by that TCM.
Instruction
Read behavior
TCM a
Hit Read from Data TCM.
Miss Read from Data TCM.
Hit Read from Data TCM.
No linefill to Data Cache fill
even if marked Cacheable.
Miss Read from Data TCM.
No linefill to Data Cache even
if marked Cacheable.
Hit Read from Data Cache.
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Table 7-4 Summary of data accesses to TCM and caches

Write behavior
Write to Data TCM. No write to the Instruction
TCM or Data Cache.
No write to level two, even if marked as
Write-Through.
Write to Data TCM. No write to Data Cache.
No write to level two even if marked as
Write-Through.
Write to Data TCM. No write to Instruction TCM.
No write to level two even if marked as
Write-Through.
Write to Data TCM.
No write to level two even if marked as
Write-Through.
Write to Data Cache.
If Write-Through, write to Instruction TCM.
Level One Memory System
7-14