ARM ARM1176JZF-S Technical Reference Manual page 512

13.10.1 Behavior of the PC in Debug state
ARM DDI 0301H
ID012310
• Instructions that access CP14 registers are always permitted in Debug state. This applies
regardless of the debug permissions and the processor mode and state. For example even
if:
— debug is only permitted in Non-secure world and in Secure User mode, SPIDEN=0,
SUIDEN=1
— the processor is in Secure user mode
• For CP15 registers in Debug state the processor behaves as follows:
— If the debugger is permitted to write to the CPSR mode bits in the current world and
change to a privileged mode, then the debugger is permitted to access the CP15
registers of that world. There is no requirement to change to a privileged mode first.
— Access to the CP15 registers of that world is then limited to the access granted to
any privileged mode in that world.
— Any attempts to perform accesses that are not permitted are treated as Undefined
Exceptions and cause the sticky Undefined bit to be set in the DSCR.
For example:
— If debug is permitted everywhere, then if the processor is stopped in any Secure
mode, including Secure User mode, it has the same access to the Secure banked
CP15 registers as any Secure privileged mode. However, if the processor is stopped
in a Non-secure mode, including Non-secure User mode, the debugger can only
directly access the Non-secure banked CP15 registers, and those CP15 registers, for
example NSAC, or bits of CP15 registers, for example the B, FI, L4 and RR bits of
the Control Register, that are not banked and are read-only in Non-secure modes are
read-only to the debugger. The debugger can write to the CPSR mode bits to switch
to Secure Monitor mode, and thereby set or clear the NS bit to read or write all CP15
registers in either bank.
— If debug is permitted only in Non-secure state and in Secure User mode, then if the
processor is stopped in Secure User mode, it has no privileged access to any CP15
registers. If the processor is stopped in any Non-secure mode, including Non-secure
User mode, then it can only access the Non-secure banked CP15 registers, and those
CP15 registers or bits of CP15 registers that are not banked and are read-only in
Non-secure modes are read-only to the debugger. The debugger cannot write to the
mode bits to change the processor into Secure Monitor mode, so cannot access any
Secure CP15 registers.
— If debug is permitted only in Non-secure state, the processor can only be stopped in
Non-secure modes, including Non-secure User mode. It can only access the
Non-secure banked CP15 registers, and those CP15 registers or bits of CP15
registers that are not banked and are read-only in Non-secure modes are read-only
to the debugger. The debugger cannot write to the mode bits to change the processor
into Secure Monitor mode, so cannot access any Secure CP15 registers.
• A DBGTAP debugger can force the processor out of Debug state by issuing a Restart
instruction. See Table 14-1 on page 14-6. The Restart command clears the DSCR[1] core
restarted flag. When the processor has actually exited Debug state, the DSCR[1] core
restarted bit is set and the DSCR[0] core halted bit and DBGACK signal are cleared.
In Debug state:
• The PC is frozen on entry to Debug state. That is, it does not increment on the execution
of ARM instructions. However, branches and instructions that modify the PC directly do
update it.
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