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15.1
About the ETM interface
15.1.1
Instruction interface
ARM DDI 0301H
ID012310
The processor trace interface port enables connection of an ETM to the processor. The ARM
Embedded Trace Macrocell (ETM) provides instruction and data trace for the ARM11 family
of processors. For more details on how the ETM interface connects to an ARM11 processor, see
the CoreSight ETM11 Technical Reference Manual.
All inputs are registered immediately inside the ETM unless specified otherwise. All outputs are
driven directly from a register unless specified otherwise. All signals are relative to CLKIN
unless specified otherwise.
The ETM interface includes the following groups of signals:
•
an instruction interface
•
a Secure control bus
•
a data address interface
•
a pipeline advance interface
•
a data value interface
•
a coprocessor interface
•
other connections to the core.
The primary sampling point for these signals is on entry to write-back. See Typical pipeline
operations on page 1-28. This ensures that instructions are traced correctly before any data
transfers associated with them, as required by the ETM protocol.
Table 15-1 lists the instruction interface signals.
Signal name
ETMIACTL[17:0]
ETMIA[31:0]
ETMIARET[31:0]
ETMIA is used for branch target address calculation.
Other than this the ETM must know, for each cycle, the current address of the instruction in
execute and the address of any branch phantom progressing through the pipeline. The processor
does not maintain the address of branch phantoms, instead it maintains the address to return to
if the branch proves to be incorrectly predicted.
The instruction interface can trace a branch phantom without an associated normal instruction.
In the case of a branch that is predicted taken, the return address, for when the branch is not
taken, is one instruction after the branch. Therefore, the branch address is:
ETMIABP = ETMIARET - <isize>
When the instruction is predicted not taken, the return address is the target of the branch.
However, because the branch was not taken, it must precede the normal instruction. Therefore,
the branch address is:
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Table 15-1 Instruction interface signals
Description
Instruction interface control signals
This is the address for:
ARM executed instruction + 8
Thumb executed instruction + 4
Java executed instruction
Address to return to if branch is incorrectly predicted
Trace Interface Port
Qualified by
-
IAValid
IABpValid
15-2
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