Table 3-121 Secure Or Non-Secure Vector Base Address Register Bit Functions; Figure 3-65 Secure Or Non-Secure Vector Base Address Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.43 c12, Secure or Non-secure Vector Base Address Register
ARM DDI 0301H
ID012310
As part of the initialization of the DMA channel, the process that uses that channel writes the
processor Context ID to the DMA Context ID Register. Where the channel is designated as a
User-accessible channel, the privileged process, that initializes the channel for use in User
mode, must write the Context ID at the same time that the software writes to the U bit for the
channel.
The process that translates VAs to physical addresses uses the ASID stored in the bottom eight
bits of the Context ID register to enable different VA maps to co-exist. Attempts to write this
register while the DMA channel is Running or Queued has no effect.
Only privileged processes can read this register. This provides anonymity of the DMA channel
usage from User processes. On a context switch, where the state of the DMA is stacked and
restored, the saved state must include this register.
If a user process attempts to access this privileged register the processor takes an Undefined
instruction trap.
The purpose of the Secure or Non-secure Vector Base Address Register is to hold the base
address for exception vectors in the Secure and Non-secure worlds. For more information, see
Exceptions on page 2-36.
The Secure or Non-secure Vector Base Address Register is:
• in CP15 c12
• a 32-bit read/write register banked in Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-65 shows the arrangement of bits in the register.
31

Figure 3-65 Secure or Non-secure Vector Base Address Register format

Table 3-121 lists how the bit values correspond with the Secure or Non-secure Vector Base
Address Register functions.

Table 3-121 Secure or Non-secure Vector Base Address Register bit functions

Bits Field name
[31:5] Vector base address
[4:0] SBZ
When an exception occurs in the Secure world, the core branches to address:
Secure Vector_Base_Address + Exception_Vector_Address.
When an exception occurs in the Non-secure world, the core branches to address:
Non-secure Vector_Base_Address + Exception_Vector_Address.
When high vectors are enabled, regardless of the value of the register the core branches to:
+ Exception_Vector_Address
0xFFFF0000
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Vector base address
Function
Determines the location that the core branches to on an exception
Holds the base address. The reset value is 0.
UNP/SBZ.
System Control Coprocessor
5 4 0
SBZ
3-121