Table 13-5 Data Transfer Register Bit Field Definitions; Figure 13-4 Dtr Format - ARM ARM1176JZF-S Technical Reference Manual

13.3.5 CP14 c6, Watchpoint Fault Address Register (WFAR)
ARM DDI 0301H
ID012310
The register accessed is dependent on the instruction used:
• writes, MCR and LDC instructions, access the wDTR
• reads, MRC and STC instructions, access the rDTR.
Note
Read and write refer to the core view.
For details of the use of these registers with the rDTRfull flag and wDTRfull flag see Debug
communications channel on page 13-42. Figure 13-4 shows the format of both the rDTR and
wDTR.
31
Table 13-5 lists the bit field definitions for rDTR and wDTR.
Bits Core view External view
[31:0] R W
[31:0] W R
The purpose of the Watchpoint Fault Address Register (WFAR) is to hold the Virtual Address
of the instruction that caused the watchpoint.
The register WFAR is:
• in CP14 c6
• a 32-bit read/write register
• accessible in privileged modes only.
When a watchpoint occurs in:
• ARM state, the WFAR contains the address of the instruction causing it plus
• Thumb state, the WFAR contains the address of the instruction causing it plus
• Jazelle state, the WFAR contains the address of the instruction causing it.
The contents of the WFAR are unaffected when a precise Data Abort or Prefetch Abort occurs.
To use the Watchpoint Fault Address Register read or write CP14 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c6
• Opcode_2 set to 0.
For example:
MRC p14, 0, <Rd>, c0, c6, 0
MCR p14, 0, <Rd>, c0, c6, 0
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Data

Table 13-5 Data Transfer Register bit field definitions

Reset value Description
- Read data transfer register, read-only
- Write data transfer register, write-only
; Read Watchpoint Fault Address Register
; Write Watchpoint Fault Address Register
Debug
0

Figure 13-4 DTR format

0x8 .
.
0x4
13-12