Table 4-1 Unaligned Access Handling - ARM ARM1176JZF-S Technical Reference Manual

4.2.3 Legacy and ARMv6 configurations
CP15 register
c1 U bit
0
0
1
1
4.2.4 Legacy data access in ARMv6 (U=0)
4.2.5 Support for unaligned data access in ARMv6 (U=1)
ARM DDI 0301H
ID012310
Table 4-1 summarizes the unaligned access handling.
CP15 register
c1 A bit
0
1
0
1
The processor emulates earlier architecture unaligned accesses to memory as follows:
• If A bit is asserted alignment faults occur for:
Halfword access
Word access
LDRD or STRD
Multiple access
• If alignment faults are enabled and the access is not aligned then the Data Abort vector is
entered with an Alignment Fault status code.
• If no alignment fault is enabled, that is, if bit 1 of CP15 Register c1, the A bit, is not set:
Byte access
Halfword access
Word access
— ARM load data rotates the aligned read data and rotates this right by the byte-offset
denoted by Address [1:0], see the ARM Architecture Reference Manual.
— ARM and Thumb load-multiple accesses always treated as aligned. No rotation of
read data.
— ARM and Thumb store word and store multiple treated as aligned. No rotation of
write data.
— ARM load and store doubleword operations treated as 64-bit aligned.
For more information, see Operation of unaligned accesses on page 4-13.
The processor memory interfaces can generate unaligned low order byte address offsets only for
halfword and single word load and store operations, and byte accesses unless the A bit is set.
These accesses produce an alignment fault if the A bit is set, and for some of the cases that
ARMv6 unaligned data access restrictions on page 4-5 describes.
If alignment faults are enabled and the access is not aligned then the Data Abort vector is entered
with an Alignment Fault status code.
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Unaligned and Mixed-endian Data Access Support
Unaligned access model
Legacy ARMv5. See Legacy data access in ARMv6 (U=0).
Legacy natural alignment check.
ARMv6 unaligned half/word access, else strict word alignment check.
ARMv6 strict half/word alignment check.
Address[0] is 1.
Address[1:0] is not b00.
Address [2:0] is not b000.
Address [1:0] is not b00.
Memory interface uses full Address [31:0].
Memory interface uses Address [31:1]. Address [0] asserted as 0.
Memory interface uses Address [31:2]. Address [1:0] asserted as 0.

Table 4-1 Unaligned access handling

4-4