Table 20-5 Fpsid Bit Fields; Figure 20-6 Floating-Point Status And Control Register - ARM ARM1176JZF-S Technical Reference Manual

Bit Meaning
[31:24] Implementer
[23] Hardware/software
[22:21] FSTMX/FLDMX
format
[20] Precisions supported
[19:16] Architecture version
[15:8] Part number
[7:4] Variant
[3:0] Revision
20.4.2 Floating-Point Status and Control Register, FPSCR
ARM DDI 0301H
ID012310
Table 20-5 lists the FPSID bit fields.
Value
0x41
A, ARM Limited
0
Hardware implementation
b00
Format 1
0
Both single-precision and double-precision data supported
b0001
VFPv2 architecture
0x20
VFP11
0xB
ARM11 VFP coprocessor
Incremented on each revision of the VFP11 coprocessor. Values for the ARM11JZF-S
product releases are:
ARM1176JZF-S r0p0:
ARM1176JZF-S r0p1 and r0p2: 0x4
ARM1176JZF-S r0p4 and r0p6: 0x5
FPSCR is a read/write register that can be accessed in both privileged and unprivileged modes.
All bits that Figure 20-6 describes as SBZ are reserved for future expansion. They must be
initialized to zeros. To ensure that these bits are not modified, code other than initialization code
must use read/modify/write techniques when writing to FPSCR. Failure to observe this rule can
cause Unpredictable results in future systems. Figure 20-6 shows the FPSCR bit fields.
31 30 29 28 27 26 25 24 23 22 21 20 19
N Z C V SBZ
DN
FZ
Rmode
Stride
SBZ
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0x3
18 16 15 14 13 12 11 10 9 8 7
LEN SBZ
IDE
IXE
UFE
OFE
DZE
IOE
IDC

Figure 20-6 Floating-Point Status and Control Register

VFP Programmer's Model

Table 20-5 FPSID bit fields

6 5 4 3 2 1 0
SBZ
IXC
UFC
OFC
DZC
IOC
20-14